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authorYork Sun <yorksun@freescale.com>2012-10-08 07:44:30 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 14:31:32 -0500
commitffd06e0231ac3fd0c5810f39f6e23527948df1c7 (patch)
tree7d648c2c312b9cc7a75c0350101aacc67afca399 /drivers/misc/ns87308.c
parent3f0997b3255c1498ac92453aa3a7a1cc95914dfd (diff)
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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