diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2018-04-11 17:07:45 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-08 09:07:34 -0400 |
| commit | 8b41464547330a39cc7e0ef87a5dd8f34db324e1 (patch) | |
| tree | ea0eb1eb7e28a3dba811bed5f1532a3acc2e296a /drivers/misc | |
| parent | 274fb461f4792431b3777874472c8bd6149e6168 (diff) | |
clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock
On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested By: Bruno Herrera <bruherrera@gmail.com>
Diffstat (limited to 'drivers/misc')
| -rw-r--r-- | drivers/misc/stm32_rcc.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index b436900d7c..dee82c0b7b 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -11,9 +11,14 @@ #include <dm/device-internal.h> #include <dm/lists.h> -struct stm32_rcc_clk stm32_rcc_clk_f4 = { +struct stm32_rcc_clk stm32_rcc_clk_f42x = { .drv_name = "stm32fx_rcc_clock", - .soc = STM32F4, + .soc = STM32F42X, +}; + +struct stm32_rcc_clk stm32_rcc_clk_f469 = { + .drv_name = "stm32fx_rcc_clock", + .soc = STM32F469, }; struct stm32_rcc_clk stm32_rcc_clk_f7 = { @@ -61,7 +66,8 @@ static const struct misc_ops stm32_rcc_ops = { }; static const struct udevice_id stm32_rcc_ids[] = { - {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f4 }, + {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x }, + {.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_clk_f469 }, {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 }, {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 }, { } |