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authorMarek Vasut <marek.vasut+renesas@gmail.com>2018-01-02 19:40:49 +0100
committerMarek Vasut <marek.vasut+renesas@gmail.com>2018-04-11 23:11:58 +0200
commit635ae6fefa0945fa5361de6f460d3dde93b143f7 (patch)
tree2e9a32747dfe2a07d0459d2bba90056c416beab3 /drivers/mmc/matsushita-common.h
parent78773f1467336f4d874a6de8e56a5092b786fde5 (diff)
mmc: matsushita-common: Handle DMA completion flag differences
The DMA READ completion flag position differs on Socionext and Renesas SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'drivers/mmc/matsushita-common.h')
-rw-r--r--drivers/mmc/matsushita-common.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mmc/matsushita-common.h b/drivers/mmc/matsushita-common.h
index a10ad202c8..8c81bbcc4b 100644
--- a/drivers/mmc/matsushita-common.h
+++ b/drivers/mmc/matsushita-common.h
@@ -96,8 +96,8 @@
#define MATSU_SD_DMA_RST_RD BIT(9)
#define MATSU_SD_DMA_RST_WR BIT(8)
#define MATSU_SD_DMA_INFO1 0x420
-#define MATSU_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
-#define MATSU_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */
+#define MATSU_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
+#define MATSU_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
#define MATSU_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
#define MATSU_SD_DMA_INFO1_MASK 0x424
#define MATSU_SD_DMA_INFO2 0x428