diff options
| author | Shivamurthy Shastri <sshivamurthy@micron.com> | 2020-07-07 22:04:13 +0200 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2020-07-20 22:29:18 +0530 |
| commit | fe48d4f99680ab99d9a6798928eb7c184c61c486 (patch) | |
| tree | 7a7ed92ffc14612dbaac4bf7a84603687beae613 /drivers/mtd/nand/spi/micron.c | |
| parent | 1f4836b0c93fe704f7cf6ec0b30b541e29ec4eb1 (diff) | |
mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies
Add device table for new Micron SPI NAND devices, which have multiple
dies.
Also, enable support to select the dies.
Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/mtd/nand/spi/micron.c')
| -rw-r--r-- | drivers/mtd/nand/spi/micron.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index fe91349999..6bacf14aaf 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -24,6 +24,14 @@ #define MICRON_CFG_CR BIT(0) +/* + * As per datasheet, die selection is done by the 6th bit of Die + * Select Register (Address 0xD0). + */ +#define MICRON_DIE_SELECT_REG 0xD0 + +#define MICRON_SELECT_DIE(x) ((x) << 6) + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -70,6 +78,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = { .rfree = micron_8_ooblayout_free, }; +static int micron_select_target(struct spinand_device *spinand, + unsigned int target) +{ + struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG, + spinand->scratchbuf); + + if (target > 1) + return -EINVAL; + + *spinand->scratchbuf = MICRON_SELECT_DIE(target); + + return spi_mem_exec_op(spinand->slave, &op); +} + static int micron_8_ecc_get_status(struct spinand_device *spinand, u8 status) { @@ -137,6 +159,17 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), + /* M79A 4Gb 3.3V */ + SPINAND_INFO("MT29F4G01ADAGD", 0x36, + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), /* M70A 4Gb 3.3V */ SPINAND_INFO("MT29F4G01ABAFD", 0x34, NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), @@ -157,6 +190,28 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), + /* M70A 8Gb 3.3V */ + SPINAND_INFO("MT29F8G01ADAFD", 0x46, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_CR_FEAT_BIT, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), + /* M70A 8Gb 1.8V */ + SPINAND_INFO("MT29F8G01ADBFD", 0x47, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_CR_FEAT_BIT, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), }; static int micron_spinand_detect(struct spinand_device *spinand) |