summaryrefslogtreecommitdiff
path: root/drivers/mtd/nand
diff options
context:
space:
mode:
authorJeff Westfahl <jeff.westfahl@ni.com>2017-11-06 00:34:46 -0800
committerMichal Simek <michal.simek@xilinx.com>2017-11-28 15:53:07 +0100
commit8000d6ea3fc99fba43e84d870632ebde3117bb35 (patch)
treed466e8db0fc284982f1a8b32cd93d5266dfca7a9 /drivers/mtd/nand
parent413ab5b0e1b88057e472ea63eb05b00eee9cf6b1 (diff)
mtd: nand: zynq: Add a config option to use 1st stage bootloader timing
In legacy method, 1st stage bootloader was used to configure the HW setting such as NAND timing. Hence, adding a config option in Zynq NAND driver for the compatibility of device that using 1st stage bootloder instead of U-boot SPL. This commit is to add config option CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS that allow NAND driver use timing values set by the 1st stage bootloader, instead of the hard-coded values in the Zynq NAND driver. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> Signed-off-by: Wilson Lee <wilson.lee@ni.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Scott Wood <oss@buserror.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/mtd/nand')
-rw-r--r--drivers/mtd/nand/Kconfig7
-rw-r--r--drivers/mtd/nand/zynq_nand.c5
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index ca9819344e..75023dc06b 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -165,6 +165,13 @@ config NAND_ZYNQ
This enables Nand driver support for Nand flash controller
found on Zynq SoC.
+config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
+ bool "Enable use of 1st stage bootloader timing for NAND"
+ depends on NAND_ZYNQ
+ help
+ This flag prevent U-boot reconfigure NAND flash controller and reuse
+ the NAND timing from 1st stage bootloader.
+
comment "Generic NAND options"
# Enhance depends when converting drivers to Kconfig which use this config
diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c
index 948f05984c..8d6a663d72 100644
--- a/drivers/mtd/nand/zynq_nand.c
+++ b/drivers/mtd/nand/zynq_nand.c
@@ -35,6 +35,8 @@
(0x1 << 4) | /* Clear interrupt */ \
(0x1 << 6)) /* Disable ECC interrupt */
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
+
/* Assuming 50MHz clock (20ns cycle time) and 3V operation */
#define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
(0x2 << 17) | /* t_ar from nand_cycles */ \
@@ -43,6 +45,7 @@
(0x2 << 8) | /* t_rea from nand_cycles */ \
(0x5 << 4) | /* t_wc from nand_cycles */ \
(0x5 << 0)) /* t_rc from nand_cycles */
+#endif
#define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
@@ -245,8 +248,10 @@ static int zynq_nand_init_nand_flash(int option)
/* disable interrupts */
writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
/* Initialize the NAND interface by setting cycles and operation mode */
writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
+#endif
if (option & NAND_BUSWIDTH_16)
writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
else