summaryrefslogtreecommitdiff
path: root/drivers/mtd/spi/sf_dataflash.c
diff options
context:
space:
mode:
authorStephen Warren <swarren@nvidia.com>2016-04-20 15:46:50 -0600
committerTom Warren <twarren@nvidia.com>2016-05-04 13:31:04 -0700
commitf5c6db84e71c60bfc7ae746bfb2cd1090d0b8765 (patch)
treeed8c5f989474332aa8d162726f2582249716098c /drivers/mtd/spi/sf_dataflash.c
parentd9b6f58efd21adf892c2507a46a0d04dd1441650 (diff)
pci: tegra: fix DM conversion issues on Tegra20
Tegra20's PCIe controller has a couple of quirks. There are workarounds in the driver for these, but they don't work after the DM conversion: 1) The PCI_CLASS value is wrong in HW. This is worked around in pci_tegra_read_config() by patching up the value read from that register. Pre-DM, the PCIe core always read this via a 16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used, so we need to check for offset 0x8 instead. Mask the offset value back to 32-bit alignment to make this work in all cases. 2) Accessing devices other than dev 1 causes a data abort. Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code called during enumeration while iterating over a bus. The DM PCIe core doesn't use this function. Instead, enhance tegra_pcie_conf_address() to validate the bdf being accessed, and refuse to access invalid devices. Since pci_skip_dev() isn't used, delete it. I've also validated that both these WARs are only needed for Tegra20, by testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in conditionally. Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model for PCI") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'drivers/mtd/spi/sf_dataflash.c')
0 files changed, 0 insertions, 0 deletions