diff options
| author | Yogesh Gaur <yogeshnarayan.gaur@nxp.com> | 2017-08-31 10:26:31 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2017-09-25 12:51:20 +0530 |
| commit | 811b6be166ee4d9eaba73ff1ae5b648d4c98b30e (patch) | |
| tree | 1d8c235dac4d726c8f79aef06c39ff4706d1ed07 /drivers/mtd/spi/spi_flash_ids.c | |
| parent | 1c631da459a82f4f82a063f5b4ff339ca5384d11 (diff) | |
mtd/spi: Add MT35XU512ABA1G12 NOR flash support
Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers/mtd/spi/spi_flash_ids.c')
| -rw-r--r-- | drivers/mtd/spi/spi_flash_ids.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index b2ab43920a..837b4124bb 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -135,6 +135,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"mt35xu512g", INFO6(0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ {"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, |