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authorSuresh Gupta <suresh.gupta@nxp.com>2017-06-05 14:37:20 +0530
committerJagan Teki <jagan@amarulasolutions.com>2017-09-25 15:45:15 +0530
commit10509987285515b0a969c39ef7374fea3545851b (patch)
tree6738dd2f648aae3e73bce28289d14b2df564ac83 /drivers/mtd/spi
parentdb10809c17c7cd8960d0c45248bbef6e76251ad7 (diff)
spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO
In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers/mtd/spi')
0 files changed, 0 insertions, 0 deletions