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authorOfer Heifetz <oferh@marvell.com>2018-08-29 11:56:02 +0300
committerStefan Roese <sr@denx.de>2018-09-19 09:00:39 +0200
commitd3859d1b5349e8105b23043e6e7158e3dc1582d4 (patch)
tree5fec6099755cf3a10b8d79c2a7cc3d23f3dea706 /drivers/mtd
parent8cdcf672c59b778f2a68a4f5d6c5f4d584f7ef54 (diff)
mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()
Since the pxa3xx_nand driver was added there has been a discrepancy in pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min. This brings us into line with the current Linux code. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 6295886eb1..8e450fb91a 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -349,9 +349,9 @@ static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
- u32 tWP_min = DIV_ROUND_UP(t->tWC_min - tWH_min, 1000);
+ u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
- u32 tRP_min = DIV_ROUND_UP(t->tRC_min - tREH_min, 1000);
+ u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
u32 tR = chip->chip_delay * 1000;
u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);