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authorStefan Chulski <stefanc@marvell.com>2017-08-09 10:37:50 +0300
committerStefan Roese <sr@denx.de>2017-08-10 08:33:02 +0200
commit783e78562d3ab55d2ca45d61b02369b198701957 (patch)
tree473f4cb8cd2754197010ab65c0b558add4c7412d /drivers/net/mvpp2.c
parent16f18d2a4decd57aa5f6eb293f163adcb69c73da (diff)
net: mvpp2x: Set BM pool high address
MVPP22 driver support 64 Bit arch and require BM pool high address configuration. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/net/mvpp2.c')
-rw-r--r--drivers/net/mvpp2.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 3fca987c29..37056c2b63 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -316,6 +316,8 @@ do { \
#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
#define MVPP22_BM_MC_RLS_REG 0x64d4
+#define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
+#define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
/* TX Scheduler registers */
#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
@@ -2594,6 +2596,10 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
lower_32_bits(bm_pool->dma_addr));
+ if (priv->hw_version == MVPP22)
+ mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
+ (upper_32_bits(bm_pool->dma_addr) &
+ MVPP22_BM_POOL_BASE_HIGH_MASK));
mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));