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authorVladimir Oltean <vladimir.oltean@nxp.com>2020-05-07 00:11:52 +0200
committerTom Rini <trini@konsulko.com>2020-05-07 11:05:00 -0400
commit4d4e4cf7798276bcb047b65cf80fde63fd347903 (patch)
treef12fdfb7245ee816c55f69124e04a261ee3e9578 /drivers/net/phy/lxt.c
parent13114f38e2ccea9386726d8b9831dfc310589548 (diff)
phy: atheros: Clarify the intention of ar8021_config
Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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