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authorQuentin Schulz <quentin.schulz@bootlin.com>2018-10-31 11:20:39 +0100
committerJoe Hershberger <joe.hershberger@ni.com>2018-11-05 10:41:59 -0600
commit05bbd676a7579545bc9c0b7ec590793bd33d2024 (patch)
tree228a6d7f746bc94533006120bf858697b4c51cab /drivers/net/pic32_eth.h
parentb5bca65e19ff63efbed8056b2651cec25192277a (diff)
net: phy: mscc: add support for VSC8574 PHY
The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX, 1000BASE-X and triple-speed copper SFP capable, can communicate with the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and can set the blinking pattern of each of its 4 LEDs, supports SyncE as well as HP Auto-MDIX detection. This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the MAC. The VSC8574 has also an internal Intel 8051 microcontroller whose firmware needs to be patched when the PHY is reset. If the 8051's firmware has the expected CRC, its patching can be skipped. The microcontroller can be accessed from any port of the PHY, though the CRC function can only be done through the PHY that is the base PHY of the package (internal address 0) due to a limitation of the firmware. The GPIO register bank is a set of registers that are common to all PHYs in the package. So any modification in any register of this bank affects all PHYs of the package. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers/net/pic32_eth.h')
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