diff options
| author | Tom Rini <trini@konsulko.com> | 2018-01-15 16:44:18 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-01-15 16:44:18 -0500 |
| commit | 8e9801c283c0e5a7ccd5c04f5ba09003d01f1591 (patch) | |
| tree | ae79033993ae3f06b581a3bd0fcd8dc36a3528eb /drivers/pci/pcie_imx.c | |
| parent | a970ee22578dce3d7596280351d3dbade561ed8c (diff) | |
| parent | 9587b0d61133c025d48ebf480aa021fc2fdd53a7 (diff) | |
Merge git://git.denx.de/u-boot-imx
Diffstat (limited to 'drivers/pci/pcie_imx.c')
| -rw-r--r-- | drivers/pci/pcie_imx.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 2900c8d9d1..ef66a1d3f4 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -517,10 +517,12 @@ static int imx6_pcie_init_phy(void) __weak int imx6_pcie_toggle_power(void) { #ifdef CONFIG_PCIE_IMX_POWER_GPIO + gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power"); gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0); mdelay(20); gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1); mdelay(20); + gpio_free(CONFIG_PCIE_IMX_POWER_GPIO); #endif return 0; } @@ -556,10 +558,12 @@ __weak int imx6_pcie_toggle_reset(void) * state due to being previously used in U-Boot. */ #ifdef CONFIG_PCIE_IMX_PERST_GPIO + gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset"); gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0); mdelay(20); gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1); mdelay(20); + gpio_free(CONFIG_PCIE_IMX_PERST_GPIO); #else puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); #endif @@ -612,6 +616,17 @@ static int imx_pcie_link_up(void) imx_pcie_regions_setup(); /* + * By default, the subordinate is set equally to the secondary + * bus (0x01) when the RC boots. + * This means that theoretically, only bus 1 is reachable from the RC. + * Force the PCIe RC subordinate to 0xff, otherwise no downstream + * devices will be detected if the enumeration is applied strictly. + */ + tmp = readl(MX6_DBI_ADDR + 0x18); + tmp |= (0xff << 16); + writel(tmp, MX6_DBI_ADDR + 0x18); + + /* * FIXME: Force the PCIe RC to Gen1 operation * The RC must be forced into Gen1 mode before bringing the link * up, otherwise no downstream devices are detected. After the |