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authorFabio Estevam <fabio.estevam@freescale.com>2015-09-10 20:45:25 -0300
committerStefano Babic <sbabic@denx.de>2015-09-13 11:04:53 +0200
commit8f6edf6d30cc22a4231c5dd97a3bd82803d8f08c (patch)
tree610afdf1e0aaedfb356b33d56aa8dd454eff9017 /drivers/pci/pcie_imx.c
parent10b347fc34aa8c5382f49126c3ce5c4e7f064d2e (diff)
pcie_imx: Use 'ms' for milliseconds
milliseconds should be written as 'ms' instead of 'mS'. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/pci/pcie_imx.c')
-rw-r--r--drivers/pci/pcie_imx.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index ca485ba90c..1568f20c1a 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -495,7 +495,7 @@ __weak int imx6_pcie_toggle_reset(void)
*
* The PCIe #PERST reset line _MUST_ be connected, otherwise your
* design does not conform to the specification. You must wait at
- * least 20 mS after de-asserting the #PERST so the EP device can
+ * least 20 ms after de-asserting the #PERST so the EP device can
* do self-initialisation.
*
* In case your #PERST pin is connected to a plain GPIO pin of the
@@ -506,7 +506,7 @@ __weak int imx6_pcie_toggle_reset(void)
* In case your #PERST toggling logic is more complex, for example
* connected via CPLD or somesuch, you can override this function
* in your board file and implement reset logic as needed. You must
- * not forget to wait at least 20 mS after de-asserting #PERST in
+ * not forget to wait at least 20 ms after de-asserting #PERST in
* this case either though.
*
* In case your #PERST line of the PCIe EP device is not connected
@@ -538,7 +538,7 @@ static int imx6_pcie_deassert_core_reset(void)
/*
* Wait for the clock to settle a bit, when the clock are sourced
- * from the CPU, we need about 30mS to settle.
+ * from the CPU, we need about 30 ms to settle.
*/
mdelay(50);