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| author | Christian Gmeiner <christian.gmeiner@gmail.com> | 2018-06-10 06:25:06 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2018-06-13 09:50:57 +0800 |
| commit | 6f95d89c71b9735a114754fc85284cca01db1006 (patch) | |
| tree | b3d87cf499cdc6f7a5d6b5e78da179593bc00ee2 /drivers/pci/pcie_layerscape_fixup.c | |
| parent | f2825f6ec0bb50e7bd9376828a32212f1961f979 (diff) | |
dm: pci: Use a 1:1 mapping for bus <-> phy addresses
If U-Boot gets used as coreboot payload all pci resources got
assigned by coreboot. If a dts without any pci ranges gets used
the dm is not able to access pci device memory. To get things
working make use of a 1:1 mapping for bus <-> phy addresses.
This change makes it possible to get the e1000 U-Boot driver
working on a sandybridge device where U-Boot is used as coreboot
payload.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pci/pcie_layerscape_fixup.c')
0 files changed, 0 insertions, 0 deletions