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authorJagannadha Sutradharudu Teki <jaganna@xilinx.com>2013-05-30 20:24:14 +0530
committerJagannadha Sutradharudu Teki <jaganna@xilinx.com>2013-06-23 22:02:50 +0530
commite3ff9d51ecf5fb00eccafa35965112e487f8b522 (patch)
tree75a9861ab24ad1b02afe9e7f88640ff720008a27 /drivers/pci
parente612ddf5939ba257f2933c7539ee39a3f760e8ce (diff)
sf: Update sf to support all sizes of flashes
Updated the spi_flash framework to handle all sizes of flashes using bank/extd addr reg facility The current implementation in spi_flash supports 3-byte address mode due to this up to 16Mbytes amount of flash is able to access for those flashes which has an actual size of > 16MB. As most of the flashes introduces a bank/extd address registers for accessing the flashes in 16Mbytes of banks if the flash size is > 16Mbytes, this new scheme will add the bank selection feature for performing write/erase operations on all flashes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pci')
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