diff options
| author | Marek Behún <marek.behun@nic.cz> | 2018-04-24 17:21:19 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2018-05-14 10:00:15 +0200 |
| commit | de49bd0e73f7d4e764f3c6b67a536de5d4e8841b (patch) | |
| tree | f4ba3829a6d7ba7917adb1018283a409706f4bd7 /drivers/phy | |
| parent | 86093582618baee4611a53764d25858ada322102 (diff) | |
phy: marvell: a3700: Set USB3 RX wait depending on ref clock
According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7
when reference clock is at 25 MHz. The specification (at least the
version I have) does not mentoin the setting for 40 MHz reference
clock, but Marvell's U-Boot sets 0xC in that case.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/marvell/comphy_a3700.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 4fb23bb547..3da9eedc23 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -382,21 +382,19 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) /* * 3. Check crystal jumper setting and program the Power and PLL * Control accordingly + * 4. Change RX wait */ if (get_ref_clk() == 40) { /* 40 MHz */ usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane); + usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane); } else { /* 25 MHz */ usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane); + usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane); } /* - * 4. Change RX wait - */ - usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane); - - /* * 5. Enable idle sync */ usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane); |