diff options
author | Heiko Stübner <heiko@sntech.de> | 2016-07-16 00:17:15 +0200 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2016-07-25 20:44:20 -0600 |
commit | 041cdb5f3d0fe778546bcf5b8b69e6b774db1d9e (patch) | |
tree | 3c3192b07e8e6acc475ed156abf62ea14b588167 /drivers/pinctrl/Kconfig | |
parent | 23c3042b106f6f5f92f4b5ec11b3d07eaf35bc06 (diff) |
cosmetic: rockchip: sort socs according to numbers
Having some sort of ordering proofed helpful in a lot of other places
already. So for a larger number of rockchip socs it might be helpful
as well instead of an ever increasing unsorted list.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pinctrl/Kconfig')
-rw-r--r-- | drivers/pinctrl/Kconfig | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 951a922f25..2972dba1f9 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -123,21 +123,21 @@ config QCA953X_PINCTRL both the GPIO definitions and pin control functions for each available multiplex function. -config ROCKCHIP_RK3288_PINCTRL - bool "Rockchip pin control driver" +config ROCKCHIP_RK3036_PINCTRL + bool "Rockchip rk3036 pin control driver" depends on DM help - Support pin multiplexing control on Rockchip rk3288 SoCs. The driver - is controlled by a device tree node which contains both the GPIO + Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is + controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available multiplex function. -config ROCKCHIP_RK3036_PINCTRL - bool "Rockchip rk3036 pin control driver" +config ROCKCHIP_RK3288_PINCTRL + bool "Rockchip pin control driver" depends on DM help - Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is - controlled by a device tree node which contains both the GPIO + Support pin multiplexing control on Rockchip rk3288 SoCs. The driver + is controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available multiplex function. |