diff options
| author | Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> | 2019-02-13 12:41:04 +0900 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-03-04 01:46:05 +0100 |
| commit | bf93f24c30bd63d94eea2fa35465e51efadf14cd (patch) | |
| tree | 0db89b0888cd2cca19589fb2ae45019c30abbdb0 /drivers/pinctrl/renesas/pfc-r8a77990.c | |
| parent | 4892e8301bd0907c6c1b87c20beaa5a4ba7989a2 (diff) | |
pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit3 when using TX0
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50,
the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected,
and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is
selected.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/pinctrl/renesas/pfc-r8a77990.c')
| -rw-r--r-- | drivers/pinctrl/renesas/pfc-r8a77990.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 992910087e..3d6cd012fd 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -1063,7 +1063,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), - PINMUX_IPSR_GPSR(IP11_15_12, TX0_A), + PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), @@ -1173,7 +1173,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), - PINMUX_IPSR_GPSR(IP13_23_20, TX0_B), + PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0), PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A), |