Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.

6 files changed, 437 insertions, 190 deletions

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f6616c5329..150c68d794 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -197,6 +197,16 @@ config PINCTRL_ROCKCHIP_RK3328
 	  the GPIO definitions and pin control functions for each available
 	  multiplex function.
 
+config PINCTRL_ROCKCHIP_RK3368
+	bool "Rockchip RK3368 pin control driver"
+	depends on DM
+	help
+	  Support pin multiplexing control on Rockchip rk3368 SoCs.
+
+	  The driver is controlled by a device tree node which contains both
+	  the GPIO definitions and pin control functions for each available
+	  multiplex function.
+
 config PINCTRL_ROCKCHIP_RK3399
 	bool "Rockchip rk3399 pin control driver"
 	depends on DM
@@ -207,6 +217,16 @@ config PINCTRL_ROCKCHIP_RK3399
 	  the GPIO definitions and pin control functions for each available
 	  multiplex function.
 
+config PINCTRL_ROCKCHIP_RV1108
+	bool "Rockchip rv1108 pin control driver"
+	depends on DM
+	help
+	  Support pin multiplexing control on Rockchip rv1108 SoC.
+
+	  The driver is controlled by a device tree node which contains
+	  both the GPIO definitions and pin control functions for each
+	  available multiplex function.
+
 config PINCTRL_SANDBOX
 	bool "Sandbox pinctrl driver"
 	depends on SANDBOX
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 69eef4c024..a1c655d537 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -9,4 +9,6 @@ obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o
+obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3368) += pinctrl_rk3368.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3399) += pinctrl_rk3399.o
+obj-$(CONFIG_PINCTRL_ROCKCHIP_RV1108) += pinctrl_rv1108.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
index 8d42584b31..9215d6c96e 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
@@ -26,19 +26,19 @@ static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id)
 {
 	switch (pwm_id) {
 	case PERIPH_ID_PWM0:
-		rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT,
+		rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
 			     GPIO0D2_PWM0 << GPIO0D2_SHIFT);
 		break;
 	case PERIPH_ID_PWM1:
-		rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT,
+		rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK,
 			     GPIO0A0_PWM1 << GPIO0A0_SHIFT);
 		break;
 	case PERIPH_ID_PWM2:
-		rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT,
+		rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK,
 			     GPIO0A1_PWM2 << GPIO0A1_SHIFT);
 		break;
 	case PERIPH_ID_PWM3:
-		rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT,
+		rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK,
 			     GPIO0D3_PWM3 << GPIO0D3_SHIFT);
 		break;
 	default:
@@ -52,23 +52,20 @@ static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id)
 	switch (i2c_id) {
 	case PERIPH_ID_I2C0:
 		rk_clrsetreg(&grf->gpio0a_iomux,
-			     GPIO0A1_MASK << GPIO0A1_SHIFT |
-			     GPIO0A0_MASK << GPIO0A0_SHIFT,
+			     GPIO0A1_MASK | GPIO0A0_MASK,
 			     GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
 			     GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
 
 		break;
 	case PERIPH_ID_I2C1:
 		rk_clrsetreg(&grf->gpio0a_iomux,
-			     GPIO0A3_MASK << GPIO0A3_SHIFT |
-			     GPIO0A2_MASK << GPIO0A2_SHIFT,
+			     GPIO0A3_MASK | GPIO0A2_MASK,
 			     GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
 			     GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
 		break;
 	case PERIPH_ID_I2C2:
 		rk_clrsetreg(&grf->gpio2c_iomux,
-			     GPIO2C5_MASK << GPIO2C5_SHIFT |
-			     GPIO2C4_MASK << GPIO2C4_SHIFT,
+			     GPIO2C5_MASK | GPIO2C4_MASK,
 			     GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
 			     GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
 
@@ -80,24 +77,20 @@ static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs)
 {
 	switch (cs) {
 	case 0:
-		rk_clrsetreg(&grf->gpio1d_iomux,
-			     GPIO1D6_MASK << GPIO1D6_SHIFT,
+		rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK,
 			     GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT);
 		break;
 	case 1:
-		rk_clrsetreg(&grf->gpio1d_iomux,
-			     GPIO1D7_MASK << GPIO1D7_SHIFT,
+		rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK,
 			     GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT);
 		break;
 	}
 	rk_clrsetreg(&grf->gpio1d_iomux,
-		     GPIO1D5_MASK << GPIO1D5_SHIFT |
-		     GPIO1D4_MASK << GPIO1D4_SHIFT,
+		     GPIO1D5_MASK | GPIO1D4_MASK,
 		     GPIO1D5_SPI_TXD << GPIO1D5_SHIFT |
 		     GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
 
-	rk_clrsetreg(&grf->gpio2a_iomux,
-		     GPIO2A0_MASK << GPIO2A0_SHIFT,
+	rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK,
 		     GPIO2A0_SPI_CLK << GPIO2A0_SHIFT);
 }
 
@@ -106,10 +99,8 @@ static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id)
 	switch (uart_id) {
 	case PERIPH_ID_UART0:
 		rk_clrsetreg(&grf->gpio0c_iomux,
-			     GPIO0C3_MASK << GPIO0C3_SHIFT |
-			     GPIO0C2_MASK << GPIO0C2_SHIFT |
-			     GPIO0C1_MASK << GPIO0C1_SHIFT |
-			     GPIO0C0_MASK << GPIO0C0_SHIFT,
+			     GPIO0C3_MASK | GPIO0C2_MASK |
+			     GPIO0C1_MASK |  GPIO0C0_MASK,
 			     GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT |
 			     GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT |
 			     GPIO0C1_UART0_SIN << GPIO0C1_SHIFT |
@@ -117,15 +108,13 @@ static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id)
 		break;
 	case PERIPH_ID_UART1:
 		rk_clrsetreg(&grf->gpio2c_iomux,
-			     GPIO2C7_MASK << GPIO2C7_SHIFT |
-			     GPIO2C6_MASK << GPIO2C6_SHIFT,
+			     GPIO2C7_MASK | GPIO2C6_MASK,
 			     GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT |
 			     GPIO2C6_UART1_SIN << GPIO2C6_SHIFT);
 		break;
 	case PERIPH_ID_UART2:
 		rk_clrsetreg(&grf->gpio1c_iomux,
-			     GPIO1C3_MASK << GPIO1C3_SHIFT |
-			     GPIO1C2_MASK << GPIO1C2_SHIFT,
+			     GPIO1C3_MASK | GPIO1C2_MASK,
 			     GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
 			     GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
 		break;
@@ -146,8 +135,7 @@ static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id)
 			     GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
 			     GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GPIO2A4_MASK << GPIO2A4_SHIFT |
-			     GPIO2A1_MASK << GPIO2A1_SHIFT,
+			     GPIO2A4_MASK | GPIO2A1_MASK,
 			     GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |
 			     GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT);
 		break;
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index b6beec5ed0..d0ffeb1f04 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -21,135 +21,28 @@ struct rk3328_pinctrl_priv {
 	struct rk3328_grf_regs *grf;
 };
 
-enum {
-	/* GRF_GPIO0A_IOMUX */
-	GRF_GPIO0A5_SEL_SHIFT	= 10,
-	GRF_GPIO0A5_SEL_MASK	= 3 << GRF_GPIO0A5_SEL_SHIFT,
-	GRF_I2C3_SCL		= 2,
-
-	GRF_GPIO0A6_SEL_SHIFT	= 12,
-	GRF_GPIO0A6_SEL_MASK	= 3 << GRF_GPIO0A6_SEL_SHIFT,
-	GRF_I2C3_SDA		= 2,
-
-	GRF_GPIO0A7_SEL_SHIFT	= 14,
-	GRF_GPIO0A7_SEL_MASK	= 3 << GRF_GPIO0A7_SEL_SHIFT,
-	GRF_EMMC_DATA0		= 2,
-
-	/* GRF_GPIO1A_IOMUX */
-	GRF_GPIO1A0_SEL_SHIFT	= 0,
-	GRF_GPIO1A0_SEL_MASK	= 0x3fff << GRF_GPIO1A0_SEL_SHIFT,
-	GRF_CARD_DATA_CLK_CMD_DETN	= 0x1555,
-
-	/* GRF_GPIO2A_IOMUX */
-	GRF_GPIO2A0_SEL_SHIFT	= 0,
-	GRF_GPIO2A0_SEL_MASK	= 3 << GRF_GPIO2A0_SEL_SHIFT,
-	GRF_UART2_TX_M1		= 1,
-
-	GRF_GPIO2A1_SEL_SHIFT	= 2,
-	GRF_GPIO2A1_SEL_MASK	= 3 << GRF_GPIO2A1_SEL_SHIFT,
-	GRF_UART2_RX_M1		= 1,
-
-	GRF_GPIO2A2_SEL_SHIFT	= 4,
-	GRF_GPIO2A2_SEL_MASK	= 3 << GRF_GPIO2A2_SEL_SHIFT,
-	GRF_PWM_IR		= 1,
-
-	GRF_GPIO2A4_SEL_SHIFT	= 8,
-	GRF_GPIO2A4_SEL_MASK	= 3 << GRF_GPIO2A4_SEL_SHIFT,
-	GRF_PWM_0		= 1,
-	GRF_I2C1_SDA,
-
-	GRF_GPIO2A5_SEL_SHIFT	= 10,
-	GRF_GPIO2A5_SEL_MASK	= 3 << GRF_GPIO2A5_SEL_SHIFT,
-	GRF_PWM_1		= 1,
-	GRF_I2C1_SCL,
-
-	GRF_GPIO2A6_SEL_SHIFT	= 12,
-	GRF_GPIO2A6_SEL_MASK	= 3 << GRF_GPIO2A6_SEL_SHIFT,
-	GRF_PWM_2		= 1,
-
-	GRF_GPIO2A7_SEL_SHIFT	= 14,
-	GRF_GPIO2A7_SEL_MASK	= 3 << GRF_GPIO2A7_SEL_SHIFT,
-	GRF_CARD_PWR_EN_M0	= 1,
-
-	/* GRF_GPIO2BL_IOMUX */
-	GRF_GPIO2BL0_SEL_SHIFT	= 0,
-	GRF_GPIO2BL0_SEL_MASK	= 0x3f << GRF_GPIO2BL0_SEL_SHIFT,
-	GRF_SPI_CLK_TX_RX_M0	= 0x15,
-
-	GRF_GPIO2BL3_SEL_SHIFT	= 6,
-	GRF_GPIO2BL3_SEL_MASK	= 3 << GRF_GPIO2BL3_SEL_SHIFT,
-	GRF_SPI_CSN0_M0		= 1,
-
-	GRF_GPIO2BL4_SEL_SHIFT	= 8,
-	GRF_GPIO2BL4_SEL_MASK	= 3 << GRF_GPIO2BL4_SEL_SHIFT,
-	GRF_SPI_CSN1_M0		= 1,
-
-	GRF_GPIO2BL5_SEL_SHIFT	= 10,
-	GRF_GPIO2BL5_SEL_MASK	= 3 << GRF_GPIO2BL5_SEL_SHIFT,
-	GRF_I2C2_SDA		= 1,
-
-	GRF_GPIO2BL6_SEL_SHIFT	= 12,
-	GRF_GPIO2BL6_SEL_MASK	= 3 << GRF_GPIO2BL6_SEL_SHIFT,
-	GRF_I2C2_SCL		= 1,
-
-	/* GRF_GPIO2D_IOMUX */
-	GRF_GPIO2D0_SEL_SHIFT	= 0,
-	GRF_GPIO2D0_SEL_MASK	= 3 << GRF_GPIO2D0_SEL_SHIFT,
-	GRF_I2C0_SCL		= 1,
-
-	GRF_GPIO2D1_SEL_SHIFT	= 2,
-	GRF_GPIO2D1_SEL_MASK	= 3 << GRF_GPIO2D1_SEL_SHIFT,
-	GRF_I2C0_SDA		= 1,
-
-	GRF_GPIO2D4_SEL_SHIFT	= 8,
-	GRF_GPIO2D4_SEL_MASK	= 0xff << GRF_GPIO2D4_SEL_SHIFT,
-	GRF_EMMC_DATA123	= 0xaa,
-
-	/* GRF_GPIO3C_IOMUX */
-	GRF_GPIO3C0_SEL_SHIFT	= 0,
-	GRF_GPIO3C0_SEL_MASK	= 0x3fff << GRF_GPIO3C0_SEL_SHIFT,
-	GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD	= 0x2aaa,
-
-	/* GRF_COM_IOMUX */
-	GRF_UART2_IOMUX_SEL_SHIFT	= 0,
-	GRF_UART2_IOMUX_SEL_MASK	= 3 << GRF_UART2_IOMUX_SEL_SHIFT,
-	GRF_UART2_IOMUX_SEL_M0		= 0,
-	GRF_UART2_IOMUX_SEL_M1,
-
-	GRF_SPI_IOMUX_SEL_SHIFT = 4,
-	GRF_SPI_IOMUX_SEL_MASK	= 3 << GRF_SPI_IOMUX_SEL_SHIFT,
-	GRF_SPI_IOMUX_SEL_M0	= 0,
-	GRF_SPI_IOMUX_SEL_M1,
-	GRF_SPI_IOMUX_SEL_M2,
-
-	GRF_CARD_IOMUX_SEL_SHIFT	= 7,
-	GRF_CARD_IOMUX_SEL_MASK		= 1 << GRF_CARD_IOMUX_SEL_SHIFT,
-	GRF_CARD_IOMUX_SEL_M0		= 0,
-	GRF_CARD_IOMUX_SEL_M1,
-};
-
 static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
 {
 	switch (pwm_id) {
 	case PERIPH_ID_PWM0:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A4_SEL_MASK,
-			     GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT);
+			     GPIO2A4_SEL_MASK,
+			     GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT);
 		break;
 	case PERIPH_ID_PWM1:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A5_SEL_MASK,
-			     GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT);
+			     GPIO2A5_SEL_MASK,
+			     GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT);
 		break;
 	case PERIPH_ID_PWM2:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A6_SEL_MASK,
-			     GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT);
+			     GPIO2A6_SEL_MASK,
+			     GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT);
 		break;
 	case PERIPH_ID_PWM3:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A2_SEL_MASK,
-			     GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT);
+			     GPIO2A2_SEL_MASK,
+			     GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT);
 		break;
 	default:
 		debug("pwm id = %d iomux error!\n", pwm_id);
@@ -162,27 +55,27 @@ static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
 	switch (i2c_id) {
 	case PERIPH_ID_I2C0:
 		rk_clrsetreg(&grf->gpio2d_iomux,
-			     GRF_GPIO2D0_SEL_MASK | GRF_GPIO2D1_SEL_MASK,
-			     GRF_I2C0_SCL << GRF_GPIO2D0_SEL_SHIFT
-			     | GRF_I2C0_SDA << GRF_GPIO2D1_SEL_SHIFT);
+			     GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK,
+			     GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT |
+			     GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT);
 		break;
 	case PERIPH_ID_I2C1:
 		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A4_SEL_MASK | GRF_GPIO2A5_SEL_MASK,
-			     GRF_I2C1_SCL << GRF_GPIO2A5_SEL_SHIFT
-			     | GRF_I2C1_SDA << GRF_GPIO2A4_SEL_SHIFT);
+			     GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK,
+			     GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT |
+			     GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT);
 		break;
 	case PERIPH_ID_I2C2:
 		rk_clrsetreg(&grf->gpio2bl_iomux,
-			     GRF_GPIO2BL5_SEL_MASK | GRF_GPIO2BL6_SEL_MASK,
-			     GRF_I2C2_SCL << GRF_GPIO2BL6_SEL_SHIFT
-			     | GRF_I2C2_SDA << GRF_GPIO2BL6_SEL_SHIFT);
+			     GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK,
+			     GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT |
+			     GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT);
 		break;
 	case PERIPH_ID_I2C3:
 		rk_clrsetreg(&grf->gpio0a_iomux,
-			     GRF_GPIO0A5_SEL_MASK | GRF_GPIO0A6_SEL_MASK,
-			     GRF_I2C3_SCL << GRF_GPIO0A5_SEL_SHIFT
-			     | GRF_I2C3_SDA << GRF_GPIO0A6_SEL_SHIFT);
+			     GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK,
+			     GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT |
+			     GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT);
 		break;
 	default:
 		debug("i2c id = %d iomux error!\n", i2c_id);
@@ -204,29 +97,35 @@ static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
 static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
 				     enum periph_id spi_id, int cs)
 {
-	rk_clrsetreg(&grf->com_iomux,
-		     GRF_SPI_IOMUX_SEL_MASK,
-		     GRF_SPI_IOMUX_SEL_M0 << GRF_SPI_IOMUX_SEL_SHIFT);
+	u32 com_iomux = readl(&grf->com_iomux);
+
+	if ((com_iomux & IOMUX_SEL_SPI_MASK) !=
+		IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) {
+		debug("driver do not support iomux other than m0\n");
+		goto err;
+	}
 
 	switch (spi_id) {
 	case PERIPH_ID_SPI0:
 		switch (cs) {
 		case 0:
 			rk_clrsetreg(&grf->gpio2bl_iomux,
-				     GRF_GPIO2BL3_SEL_MASK,
-				     GRF_SPI_CSN0_M0 << GRF_GPIO2BL3_SEL_SHIFT);
+				     GPIO2BL3_SEL_MASK,
+				     GPIO2BL3_SPI_CSN0_M0
+				     << GPIO2BL3_SEL_SHIFT);
 			break;
 		case 1:
 			rk_clrsetreg(&grf->gpio2bl_iomux,
-				     GRF_GPIO2BL4_SEL_MASK,
-				     GRF_SPI_CSN1_M0 << GRF_GPIO2BL4_SEL_SHIFT);
+				     GPIO2BL4_SEL_MASK,
+				     GPIO2BL4_SPI_CSN1_M0
+				     << GPIO2BL4_SEL_SHIFT);
 			break;
 		default:
 			goto err;
 		}
 		rk_clrsetreg(&grf->gpio2bl_iomux,
-			     GRF_GPIO2BL0_SEL_MASK,
-			     GRF_SPI_CLK_TX_RX_M0 << GRF_GPIO2BL0_SEL_SHIFT);
+			     GPIO2BL0_SEL_MASK,
+			     GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT);
 		break;
 	default:
 		goto err;
@@ -240,18 +139,17 @@ err:
 
 static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
 {
+	u32 com_iomux = readl(&grf->com_iomux);
+
 	switch (uart_id) {
 	case PERIPH_ID_UART2:
 		break;
-		/* uart2 iomux select m1 */
-		rk_clrsetreg(&grf->com_iomux,
-			     GRF_UART2_IOMUX_SEL_MASK,
-			     GRF_UART2_IOMUX_SEL_M1
-			     << GRF_UART2_IOMUX_SEL_SHIFT);
-		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A0_SEL_MASK | GRF_GPIO2A1_SEL_MASK,
-			     GRF_UART2_TX_M1 << GRF_GPIO2A0_SEL_SHIFT |
-			     GRF_UART2_RX_M1 << GRF_GPIO2A1_SEL_SHIFT);
+		if (com_iomux & IOMUX_SEL_UART2_MASK)
+			rk_clrsetreg(&grf->gpio2a_iomux,
+				     GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
+				     GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
+				     GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
+
 		break;
 	case PERIPH_ID_UART0:
 	case PERIPH_ID_UART1:
@@ -266,31 +164,37 @@ static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
 static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
 					int mmc_id)
 {
+	u32 com_iomux = readl(&grf->com_iomux);
+
 	switch (mmc_id) {
 	case PERIPH_ID_EMMC:
 		rk_clrsetreg(&grf->gpio0a_iomux,
-			     GRF_GPIO0A7_SEL_MASK,
-			     GRF_EMMC_DATA0 << GRF_GPIO0A7_SEL_SHIFT);
+			     GPIO0A7_SEL_MASK,
+			     GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio2d_iomux,
-			     GRF_GPIO2D4_SEL_MASK,
-			     GRF_EMMC_DATA123 << GRF_GPIO2D4_SEL_SHIFT);
+			     GPIO2D4_SEL_MASK,
+			     GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio3c_iomux,
-			     GRF_GPIO3C0_SEL_MASK,
-			     GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD
-			     << GRF_GPIO3C0_SEL_SHIFT);
+			     GPIO3C0_SEL_MASK,
+			     GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD
+			     << GPIO3C0_SEL_SHIFT);
 		break;
 	case PERIPH_ID_SDCARD:
-		/* sdcard iomux select m0 */
-		rk_clrsetreg(&grf->com_iomux,
-			     GRF_CARD_IOMUX_SEL_MASK,
-			     GRF_CARD_IOMUX_SEL_M0 << GRF_CARD_IOMUX_SEL_SHIFT);
-		rk_clrsetreg(&grf->gpio2a_iomux,
-			     GRF_GPIO2A7_SEL_MASK,
-			     GRF_CARD_PWR_EN_M0 << GRF_GPIO2A7_SEL_SHIFT);
+		/* SDMMC_PWREN use GPIO and init as regulator-fiexed  */
+		if (com_iomux & IOMUX_SEL_SDMMC_MASK)
+			rk_clrsetreg(&grf->gpio0d_iomux,
+				     GPIO0D6_SEL_MASK,
+				     GPIO0D6_SDMMC0_PWRENM1
+				     << GPIO0D6_SEL_SHIFT);
+		else
+			rk_clrsetreg(&grf->gpio2a_iomux,
+				     GPIO2A7_SEL_MASK,
+				     GPIO2A7_SDMMC0_PWRENM0
+				     << GPIO2A7_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio1a_iomux,
-			     GRF_GPIO1A0_SEL_MASK,
-			     GRF_CARD_DATA_CLK_CMD_DETN
-			     << GRF_GPIO1A0_SEL_SHIFT);
+			     GPIO1A0_SEL_MASK,
+			     GPIO1A0_CARD_DATA_CLK_CMD_DETN
+			     << GPIO1A0_SEL_SHIFT);
 		break;
 	default:
 		debug("mmc id = %d iomux error!\n", mmc_id);
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
new file mode 100644
index 0000000000..bdf0758c0c
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/periph.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3368_pinctrl_priv {
+	struct rk3368_grf *grf;
+	struct rk3368_pmu_grf *pmugrf;
+};
+
+static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
+				       int uart_id)
+{
+	struct rk3368_grf *grf = priv->grf;
+	struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
+
+	switch (uart_id) {
+	case PERIPH_ID_UART2:
+		rk_clrsetreg(&grf->gpio2a_iomux,
+			     GPIO2A6_MASK | GPIO2A5_MASK,
+			     GPIO2A6_UART2_SIN << GPIO2A6_SHIFT |
+			     GPIO2A5_UART2_SOUT << GPIO2A5_SHIFT);
+		break;
+	case PERIPH_ID_UART0:
+		break;
+	case PERIPH_ID_UART1:
+		break;
+	case PERIPH_ID_UART3:
+		break;
+	case PERIPH_ID_UART4:
+		rk_clrsetreg(&pmugrf->gpio0d_iomux,
+			     GPIO0D0_MASK | GPIO0D1_MASK |
+			     GPIO0D2_MASK | GPIO0D3_MASK,
+			     GPIO0D0_GPIO << GPIO0D0_SHIFT |
+			     GPIO0D1_GPIO << GPIO0D1_SHIFT |
+			     GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
+			     GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
+		break;
+	default:
+		debug("uart id = %d iomux error!\n", uart_id);
+		break;
+	}
+}
+
+static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+	struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
+
+	debug("%s: func=%d, flags=%x\n", __func__, func, flags);
+	switch (func) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+	case PERIPH_ID_UART4:
+		pinctrl_rk3368_uart_config(priv, func);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
+					struct udevice *periph)
+{
+	u32 cell[3];
+	int ret;
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
+				   "interrupts", cell, ARRAY_SIZE(cell));
+	if (ret < 0)
+		return -EINVAL;
+
+	switch (cell[1]) {
+	case 59:
+		return PERIPH_ID_UART4;
+	case 58:
+		return PERIPH_ID_UART3;
+	case 57:
+		return PERIPH_ID_UART2;
+	case 56:
+		return PERIPH_ID_UART1;
+	case 55:
+		return PERIPH_ID_UART0;
+	}
+
+	return -ENOENT;
+}
+
+static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
+					   struct udevice *periph)
+{
+	int func;
+
+	func = rk3368_pinctrl_get_periph_id(dev, periph);
+	if (func < 0)
+		return func;
+
+	return rk3368_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk3368_pinctrl_ops = {
+	.set_state_simple	= rk3368_pinctrl_set_state_simple,
+	.request	= rk3368_pinctrl_request,
+	.get_periph_id	= rk3368_pinctrl_get_periph_id,
+};
+
+static int rk3368_pinctrl_probe(struct udevice *dev)
+{
+	struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
+	int ret = 0;
+
+	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+	debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
+
+	return ret;
+}
+
+static const struct udevice_id rk3368_pinctrl_ids[] = {
+	{ .compatible = "rockchip,rk3368-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3368) = {
+	.name		= "rockchip_rk3368_pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= rk3368_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
+	.ops		= &rk3368_pinctrl_ops,
+	.bind		= dm_scan_fdt_dev,
+	.probe		= rk3368_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c b/drivers/pinctrl/rockchip/pinctrl_rv1108.c
new file mode 100644
index 0000000000..bdf3910a88
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rv1108.c
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rv1108.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rv1108_pinctrl_priv {
+	struct rv1108_grf *grf;
+};
+
+static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
+{
+	switch (uart_id) {
+	case PERIPH_ID_UART0:
+		rk_clrsetreg(&grf->gpio3a_iomux,
+			     GPIO3A6_MASK | GPIO3A5_MASK,
+			     GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
+			     GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
+		break;
+	case PERIPH_ID_UART1:
+		rk_clrsetreg(&grf->gpio1d_iomux,
+			     GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK |
+			     GPIO1D0_MASK,
+			     GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT |
+			     GPIO1D2_UART0_SIN << GPIO1D2_SHIFT |
+			     GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT |
+			     GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT);
+		break;
+	case PERIPH_ID_UART2:
+		rk_clrsetreg(&grf->gpio2d_iomux,
+			     GPIO2D2_MASK | GPIO2D1_MASK,
+			     GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
+			     GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
+		break;
+	}
+}
+
+static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func)
+{
+	rk_clrsetreg(&grf->gpio1b_iomux,
+		     GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK |
+		     GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK,
+		     GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT |
+		     GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT |
+		     GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT |
+		     GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT |
+		     GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT |
+		     GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT);
+	rk_clrsetreg(&grf->gpio1c_iomux,
+		     GPIO1C5_MASK | GPIO1C4_MASK |
+		     GPIO1C3_MASK | GPIO1C2_MASK,
+		     GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT |
+		     GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT |
+		     GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT |
+		     GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT);
+	writel(0xffff57f5, &grf->gpio1b_drv);
+}
+
+static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf)
+{
+	rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK |
+		     GPIO2A1_MASK | GPIO2A0_MASK,
+		     GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT |
+		     GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT |
+		     GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT |
+		     GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT);
+	rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK,
+		     GPIO2B7_SFC_CLK << GPIO2B7_SHIFT |
+		     GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT);
+}
+
+static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+	struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
+
+	switch (func) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+		pinctrl_rv1108_uart_config(priv->grf, func);
+		break;
+	case PERIPH_ID_GMAC:
+		pinctrl_rv1108_gmac_config(priv->grf, func);
+	case PERIPH_ID_SFC:
+		pinctrl_rv1108_sfc_config(priv->grf);
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int rv1108_pinctrl_get_periph_id(struct udevice *dev,
+					struct udevice *periph)
+{
+	u32 cell[3];
+	int ret;
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
+				   "interrupts", cell, ARRAY_SIZE(cell));
+	if (ret < 0)
+		return -EINVAL;
+
+	switch (cell[1]) {
+	case 11:
+		return PERIPH_ID_SDCARD;
+	case 13:
+		return PERIPH_ID_EMMC;
+	case 19:
+		return PERIPH_ID_GMAC;
+	case 30:
+		return PERIPH_ID_I2C0;
+	case 31:
+		return PERIPH_ID_I2C1;
+	case 32:
+		return PERIPH_ID_I2C2;
+	case 39:
+		return PERIPH_ID_PWM0;
+	case 44:
+		return PERIPH_ID_UART0;
+	case 45:
+		return PERIPH_ID_UART1;
+	case 46:
+		return PERIPH_ID_UART2;
+	case 56:
+		return PERIPH_ID_SFC;
+	}
+
+	return -ENOENT;
+}
+
+static int rv1108_pinctrl_set_state_simple(struct udevice *dev,
+					   struct udevice *periph)
+{
+	int func;
+
+	func = rv1108_pinctrl_get_periph_id(dev, periph);
+	if (func < 0)
+		return func;
+
+	return rv1108_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rv1108_pinctrl_ops = {
+	.set_state_simple	= rv1108_pinctrl_set_state_simple,
+	.request		= rv1108_pinctrl_request,
+	.get_periph_id		= rv1108_pinctrl_get_periph_id,
+};
+
+static int rv1108_pinctrl_probe(struct udevice *dev)
+{
+	struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
+
+	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	return 0;
+}
+
+static const struct udevice_id rv1108_pinctrl_ids[] = {
+	{.compatible = "rockchip,rv1108-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_rv1108) = {
+	.name           = "pinctrl_rv1108",
+	.id             = UCLASS_PINCTRL,
+	.of_match       = rv1108_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv),
+	.ops            = &rv1108_pinctrl_ops,
+	.bind           = dm_scan_fdt_dev,
+	.probe          = rv1108_pinctrl_probe,
+};