diff options
| author | YouMin Chen <cym@rock-chips.com> | 2019-11-15 11:04:43 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-11-17 16:23:56 +0800 |
| commit | 39edfaa758a1f875dfed8d8749e4c84c21db6e2a (patch) | |
| tree | 7a06a332a20fa7e50a2452080c78acfc6f9a0fba /drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc | |
| parent | c525bb42aabd1c52c758b64758a9d5fc12e52d01 (diff) | |
ram: px30: add sdram driver
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.
For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc')
| -rw-r--r-- | drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc b/drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc new file mode 100644 index 0000000000..f694a0e5b0 --- /dev/null +++ b/drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc @@ -0,0 +1,74 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0, + }, + { + {0x290a060a}, + {0x08020303}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x0000021a}, + 0x000000ff + } + }, + { + .ddr_freq = 333, + .dramtype = LPDDR3, + .num_channels = 1, + .stride = 0, + .odt = 0, + }, + { + { + {0x00000000, 0x43041008}, /* MSTR */ + {0x00000064, 0x00140023}, /* RFSHTMG */ + {0x000000d0, 0x00220002}, /* INIT0 */ + {0x000000d4, 0x00010000}, /* INIT1 */ + {0x000000d8, 0x00000703}, /* INIT2 */ + {0x000000dc, 0x00830004}, /* INIT3 */ + {0x000000e0, 0x00010000}, /* INIT4 */ + {0x000000e4, 0x00070003}, /* INIT5 */ + {0x000000f4, 0x000f012f}, /* RANKCTL */ + {0x00000100, 0x06090b07}, /* DRAMTMG0 */ + {0x00000104, 0x0002020b}, /* DRAMTMG1 */ + {0x00000108, 0x02030506}, /* DRAMTMG2 */ + {0x0000010c, 0x00505000}, /* DRAMTMG3 */ + {0x00000110, 0x03020204}, /* DRAMTMG4 */ + {0x00000114, 0x01010303}, /* DRAMTMG5 */ + {0x00000118, 0x02020003}, /* DRAMTMG6 */ + {0x00000120, 0x00000303}, /* DRAMTMG8 */ + {0x00000138, 0x00000025}, /* DRAMTMG14 */ + {0x00000180, 0x003c000f}, /* ZQCTL0 */ + {0x00000184, 0x00900000}, /* ZQCTL1 */ + {0x00000190, 0x07020000}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0900090c}, /* ODTCFG */ + {0x00000244, 0x00000101}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000000b}, /* PHYREG01 */ + {0x00000028, 0x00000006}, /* PHYREG0A */ + {0x0000002c, 0x00000000}, /* PHYREG0B */ + {0x00000030, 0x00000003}, /* PHYREG0C */ + {0xffffffff, 0xffffffff} + } + } +}, |