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authorJagan Teki <jagan@amarulasolutions.com>2019-07-16 17:27:12 +0530
committerKever Yang <kever.yang@rock-chips.com>2019-07-20 23:59:44 +0800
commit5cbc8669819a69c22a50d2fb22c9d4962c8bbad5 (patch)
treec0ecd11723228a17348918bc330e0ec1b8063d11 /drivers/ram/rockchip
parent6cbd2426b34e7430b0733ab9a912d378c027b647 (diff)
ram: rk3399: Don't wait for PLL lock in lpddr4
lpddr4 has PLL bypass mode during phy initialization phase, which does all pll configurations. So no need to wait explicitly during pctl config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/ram/rockchip')
-rw-r--r--drivers/ram/rockchip/sdram_rk3399.c26
1 files changed, 16 insertions, 10 deletions
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 35de76adb3..6f6f38214d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -570,16 +570,22 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
setbits_le32(&denali_pi[0], START);
setbits_le32(&denali_ctl[0], START);
- /* Waiting for phy DLL lock */
- while (1) {
- tmp = readl(&denali_phy[920]);
- tmp1 = readl(&denali_phy[921]);
- tmp2 = readl(&denali_phy[922]);
- if ((((tmp >> 16) & 0x1) == 0x1) &&
- (((tmp1 >> 16) & 0x1) == 0x1) &&
- (((tmp1 >> 0) & 0x1) == 0x1) &&
- (((tmp2 >> 0) & 0x1) == 0x1))
- break;
+ /**
+ * LPDDR4 use PLL bypass mode for init
+ * not need to wait for the PLL to lock
+ */
+ if (params->base.dramtype != LPDDR4) {
+ /* Waiting for phy DLL lock */
+ while (1) {
+ tmp = readl(&denali_phy[920]);
+ tmp1 = readl(&denali_phy[921]);
+ tmp2 = readl(&denali_phy[922]);
+ if ((((tmp >> 16) & 0x1) == 0x1) &&
+ (((tmp1 >> 16) & 0x1) == 0x1) &&
+ (((tmp1 >> 0) & 0x1) == 0x1) &&
+ (((tmp2 >> 0) & 0x1) == 0x1))
+ break;
+ }
}
copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);