diff options
| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:27:23 +0530 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-20 23:59:44 +0800 |
| commit | aa30aae8b4e8c871a263ad67c4b4fdca236bf7c1 (patch) | |
| tree | d4e52f1aa4edc2b4566e4acf488d81883df184a6 /drivers/ram/rockchip | |
| parent | 2fb2de33b2d89442d08a7d69f6afb9c7e46aa992 (diff) | |
ram: rk3399: Add tsel control clock drive
tsel contrl clock drives are required to configure PHY
929, 939 controls drive settings.
Add support for these control clock for all dramtype
sdrams.
Thse control clock drives are configure via tsel_ckcs_select_p
and tsel_ckcs_select_n variables.
tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as
tsel_ckcs_select_p is retrived from IO settings for lpddr4
and rest uses PHY_DRV_ODT_34_3.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/ram/rockchip')
| -rw-r--r-- | drivers/ram/rockchip/sdram_rk3399.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 5a2d50f982..d958e9ddf7 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -560,6 +560,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_select_n, tsel_rd_select_n; u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; + u32 tsel_ckcs_select_p, tsel_ckcs_select_n; struct io_setting *io = NULL; u32 reg_value; @@ -577,6 +578,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = io->wr_ca_drv; tsel_wr_select_ca_n = PHY_DRV_ODT_40; + + tsel_ckcs_select_p = io->wr_ckcs_drv; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; @@ -589,6 +593,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = PHY_DRV_ODT_48; tsel_wr_select_ca_n = PHY_DRV_ODT_48; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -601,6 +608,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } if (params->base.odt == 1) @@ -659,10 +669,12 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[935], 0xff, reg_value); /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ - clrsetbits_le32(&denali_phy[939], 0xff, reg_value); + clrsetbits_le32(&denali_phy[939], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ - clrsetbits_le32(&denali_phy[929], 0xff, reg_value); + clrsetbits_le32(&denali_phy[929], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ clrsetbits_le32(&denali_phy[924], 0xff, |