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authorPatrick Delaunay <patrick.delaunay@st.com>2019-04-10 14:09:26 +0200
committerPatrice Chotard <patrice.chotard@st.com>2019-05-23 11:38:11 +0200
commit1767ac2d1f7fadc0780f95243906dda7553ac77a (patch)
tree7244cadea8e21eac617c7e5ccc9271232717998a /drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
parent53bb8316583bf2206918457ec049b001d5b40a0f (diff)
stm32mp1: ram: add support for LPDDR2/LPDDR3
Manage power supply configuration for board using stpmic1 with LPDDR2 or with LPDDR3: + VDD_DDR1 = 1.8V with BUCK3 (bypass if possible) + VDD_DDR2 = 1.2V with BUCK2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'drivers/ram/stm32mp1/stm32mp1_ddr_regs.h')
-rw-r--r--drivers/ram/stm32mp1/stm32mp1_ddr_regs.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
index a606b2bcbe..97f268e66d 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
@@ -234,6 +234,8 @@ struct stm32mp1_ddrphy {
/* DDRCTRL REGISTERS */
#define DDRCTRL_MSTR_DDR3 BIT(0)
+#define DDRCTRL_MSTR_LPDDR2 BIT(2)
+#define DDRCTRL_MSTR_LPDDR3 BIT(3)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12)