diff options
| author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-03-06 11:14:09 +0100 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-03-24 14:23:18 +0100 |
| commit | b604a41c6bcfb6273e7478089ff3e7b65e233645 (patch) | |
| tree | dc7f3cd77c1fecd3024f0eeb51a281a007fd530e /drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | |
| parent | 8c9ce0807545976c4080621be80dfb02b4ead400 (diff) | |
ram: stm32mp1_ddr: fix self refresh disable during DQS training
DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step, not
to enter in self refresh mode during the execution of this phase.
Depending on settings, it can be set after the DQS training.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'drivers/ram/stm32mp1/stm32mp1_ddr_regs.h')
| -rw-r--r-- | drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h index 9d33186b3a..afd93c518e 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -260,6 +260,7 @@ struct stm32mp1_ddrphy { #define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) +#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) #define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) #define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) |