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authorSimon Glass <sjg@chromium.org>2020-02-03 07:36:16 -0700
committerSimon Glass <sjg@chromium.org>2020-02-05 19:33:46 -0700
commit336d4615f8fa774557d14f9b3245daa9e5fe3dbc (patch)
tree7a4d2d33113f44238d64e7e409fd3aafef63c2ed /drivers/ram
parent61b29b82683863a970fd4609a7c58512872616bc (diff)
dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/ram')
-rw-r--r--drivers/ram/k3-am654-ddrss.c1
-rw-r--r--drivers/ram/k3-j721e/k3-j721e-ddrss.c1
-rw-r--r--drivers/ram/stm32_sdram.c1
3 files changed, 3 insertions, 0 deletions
diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c
index 7015d8cfe7..8cf74861a8 100644
--- a/drivers/ram/k3-am654-ddrss.c
+++ b/drivers/ram/k3-am654-ddrss.c
@@ -14,6 +14,7 @@
#include <power-domain.h>
#include <dm.h>
#include <asm/arch/sys_proto.h>
+#include <dm/device_compat.h>
#include <power/regulator.h>
#include "k3-am654-ddrss.h"
diff --git a/drivers/ram/k3-j721e/k3-j721e-ddrss.c b/drivers/ram/k3-j721e/k3-j721e-ddrss.c
index a9b7d40890..352483c4d7 100644
--- a/drivers/ram/k3-j721e/k3-j721e-ddrss.c
+++ b/drivers/ram/k3-j721e/k3-j721e-ddrss.c
@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <power-domain.h>
#include <wait_bit.h>
+#include <dm/device_compat.h>
#include "lpddr4_obj_if.h"
#include "lpddr4_if.h"
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index f6cac8eb90..2d03333b1b 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#define MEM_MODE_MASK GENMASK(2, 0)
#define SWP_FMC_OFFSET 10