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| author | Jian Li <jian.li@nxp.com> | 2020-02-27 09:40:10 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-07-14 15:23:46 +0800 |
| commit | 3f63d27c177a84dd97f77fb843ff4e4c6d7d45eb (patch) | |
| tree | be1e34e84d79011ff9711c723f3d6706f45a40c1 /drivers/reset/sandbox-reset.c | |
| parent | 5865d14dde8f60f678e144e432a5e5ad223915d0 (diff) | |
imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit
In uMCTL2 Databook, for LPDDR4, it is recommended to set
this register to 1. This can avoid ddr bandwidth is lower
after booting with running for a while.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/reset/sandbox-reset.c')
0 files changed, 0 insertions, 0 deletions