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authorLey Foon Tan <ley.foon.tan@intel.com>2020-01-10 13:48:37 +0800
committerMarek Vasut <marex@denx.de>2020-02-03 09:26:14 +0100
commit9e6082198acca5371dded5fcbede7a53ff4a7ec8 (patch)
treeaf6a8bf98a4dd0ecc55bd584cb524cc20d8de6f6 /drivers/reset
parent31a790bee939e227dfc7e6a6a323b2b13180707f (diff)
reset: socfpga: Poll for reset status after deassert reset
In Cyclone 5 SoC platform, the first USB probing is failed but second probing is success. DWC2 USB driver read gsnpsid register right after de-assert reset, but controller is not ready yet and it returns gsnpsid 0. Polling reset status after de-assert reset to solve the issue. Retry with this fix more than 10 times without issue. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'drivers/reset')
-rw-r--r--drivers/reset/reset-socfpga.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 93ec9cfdb6..105ce94c71 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -18,6 +18,7 @@
#include <dm/of_access.h>
#include <env.h>
#include <reset-uclass.h>
+#include <wait_bit.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
@@ -80,7 +81,10 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
int offset = id % (reg_width * BITS_PER_BYTE);
clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
- return 0;
+
+ return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT),
+ BIT(offset),
+ false, 500, false);
}
static int socfpga_reset_request(struct reset_ctl *reset_ctl)