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authorVladimir Barinov <vladimir.barinov@cogentembedded.com>2015-02-14 01:05:18 +0300
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2015-02-25 13:53:37 +0900
commit2cbb17c0e941db629ff2d363c7fef69e47fb7d92 (patch)
tree3c07f99e7c1b252c0eca29d6a34da9712b008517 /drivers/serial/serial_sh.h
parent89f99a62c1a50d1bad75de315c454c9cf56b2d8d (diff)
serial: sh: fix internal clock source on SCIF
The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows: BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1, the prescaler is 0 due to SCSMR settings, hence n=0 Also SCSCR must be set to use internal or external clock source. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/serial/serial_sh.h')
-rw-r--r--drivers/serial/serial_sh.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 528aa7351d..941e6eda4c 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -227,7 +227,8 @@ struct uart_port {
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ORER 0x0001
-# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
+# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
+ /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
# error CPU subtype not defined
#endif
@@ -742,7 +743,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */
+#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif