Merge remote-tracking branch 'u-boot/master'

3 files changed, 35 insertions, 32 deletions

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index ccb80d2d1d..ddb725d326 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -111,7 +111,7 @@ config DEBUG_UART_SHIFT
 
 config ROCKCHIP_SERIAL
 	bool "Rockchip on-chip UART support"
-	depends on ARCH_UNIPHIER && DM_SERIAL
+	depends on ARCH_ROCKCHIP && DM_SERIAL
 	help
 	  Select this to enable a debug UART for Rockchip devices. This uses
 	  the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index ecf3bc0240..3a5c1d0eaa 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -80,13 +80,6 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs,
 		writel(0, &regs->pl010_cr);
 		break;
 	case TYPE_PL011:
-#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
-		/* Empty RX fifo if necessary */
-		if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
-			while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
-				readl(&regs->dr);
-		}
-#endif
 		/* disable everything */
 		writel(0, &regs->pl011_cr);
 		break;
@@ -105,21 +98,6 @@ static int pl011_set_line_control(struct pl01x_regs *regs)
 	 * control register write
 	 */
 	lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
-#ifdef CONFIG_PL011_SERIAL_RLCR
-	{
-		int i;
-
-		/*
-		 * Program receive line control register after waiting
-		 * 10 bus cycles.  Delay be writing to readonly register
-		 * 10 times
-		 */
-		for (i = 0; i < 10; i++)
-			writel(lcr, &regs->fr);
-
-		writel(lcr, &regs->pl011_rlcr);
-	}
-#endif
 	writel(lcr, &regs->pl011_lcrh);
 	return 0;
 }
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 941e6eda4c..cbc2929435 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -226,7 +226,11 @@ struct uart_port {
 # define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
-# define SCIF_ORER	0x0001
+# if defined(CONFIG_SCIF_A)
+#  define SCIF_ORER	0x0200
+# else
+#  define SCIF_ORER	0x0001
+# endif
 # define SCSCR_INIT(port)	(port->clk_mode == EXT_CLK ? 0x32 : 0x30)
 				/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
 #else
@@ -306,7 +310,11 @@ struct uart_port {
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
-# define SCIF_RFDC_MASK	0x003f
+# if defined(CONFIG_SCIF_A)
+#  define SCIF_RFDC_MASK	0x007f
+# else
+#  define SCIF_RFDC_MASK	0x001f
+# endif
 #else
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 # define SCIF_RFDC_MASK 0x001f
@@ -557,6 +565,25 @@ SCIF_FNS(SCFCR,  0x18, 16)
 SCIF_FNS(SCFDR,  0x1c, 16)
 SCIF_FNS(SCLSR,  0x24, 16)
 SCIF_FNS(DL,	 0x00,  0) /* dummy */
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+/* SCIFA and SCIF register offsets and size */
+SCIx_FNS(SCSMR,  0,  0, 0x00, 16, 0,  0, 0x00, 16, 0,  0)
+SCIx_FNS(SCBRR,  0,  0, 0x04,  8, 0,  0, 0x04,  8, 0,  0)
+SCIx_FNS(SCSCR,  0,  0, 0x08, 16, 0,  0, 0x08, 16, 0,  0)
+SCIx_FNS(SCxTDR, 0,  0, 0x20,  8, 0,  0, 0x0C,  8, 0,  0)
+SCIx_FNS(SCxSR,  0,  0, 0x14, 16, 0,  0, 0x10, 16, 0,  0)
+SCIx_FNS(SCxRDR, 0,  0, 0x24,  8, 0,  0, 0x14,  8, 0,  0)
+SCIF_FNS(SCFCR,  0,  0, 0x18, 16)
+SCIF_FNS(SCFDR,  0,  0, 0x1C, 16)
+SCIF_FNS(SCSPTR, 0,  0, 0x20, 16)
+SCIF_FNS(DL,     0,  0, 0x30, 16)
+SCIF_FNS(CKS,    0,  0, 0x34, 16)
+#if defined(CONFIG_SCIF_A)
+SCIF_FNS(SCLSR,  0,  0, 0x14, 16)
+#else
+SCIF_FNS(SCLSR,  0,  0, 0x24, 16)
+#endif
 #else
 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
@@ -594,14 +621,8 @@ SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 #endif
 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 #endif
-#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
-SCIF_FNS(DL,				0,  0, 0x30, 16)
-SCIF_FNS(CKS,				0,  0, 0x34, 16)
-#else
 SCIF_FNS(DL,				0,  0, 0x0,  0) /* dummy */
 #endif
-#endif
 #define sci_in(port, reg) sci_##reg##_in(port)
 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 
@@ -743,7 +764,11 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
-#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
+ #if defined(CONFIG_SCIF_A)
+  #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
+ #else
+  #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
+ #endif
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif