Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'

7 files changed, 437 insertions, 135 deletions

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a0b6e02b54..1686a1f951 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -2,8 +2,69 @@ config DM_SERIAL
 	bool "Enable Driver Model for serial drivers"
 	depends on DM
 	help
-	  If you want to use driver model for serial drivers, say Y.
-	  To use legacy serial drivers, say N.
+	  Enable driver model for serial. This replaces
+	  drivers/serial/serial.c with the serial uclass, which
+	  implements serial_putc() etc. The uclass interface is
+	  defined in include/serial.h.
+
+config DEBUG_UART
+	bool "Enable an early debug UART for debugging"
+	help
+	  The debug UART is intended for use very early in U-Boot to debug
+	  problems when an ICE or other debug mechanism is not available.
+
+	  To use it you should:
+	  - Make sure your UART supports this interface
+	  - Enable CONFIG_DEBUG_UART
+	  - Enable the CONFIG for your UART to tell it to provide this interface
+	        (e.g. CONFIG_DEBUG_UART_NS16550)
+	  - Define the required settings as needed (see below)
+	  - Call debug_uart_init() before use
+	  - Call debug_uart_putc() to output a character
+
+	  Depending on your platform it may be possible to use this UART before
+	  a stack is available.
+
+	  If your UART does not support this interface you can probably add
+	  support quite easily. Remember that you cannot use driver model and
+	  it is preferred to use no stack.
+
+	  You must not use this UART once driver model is working and the
+	  serial drivers are up and running (done in serial_init()). Otherwise
+	  the drivers may conflict and you will get strange output.
+
+choice
+	prompt "Select which UART will provide the debug UART"
+	depends on DEBUG_UART
+
+config DEBUG_UART_NS16550
+	bool "ns16550"
+	help
+	  Select this to enable a debug UART using the ns16550 driver. You
+	  will need to provide parameters to make this work. The driver will
+	  be available until the real driver model serial is running.
+
+endchoice
+
+config DEBUG_UART_BASE
+	hex "Base address of UART"
+	depends on DEBUG_UART
+	help
+	  This is the base address of your UART for memory-mapped UARTs.
+
+	  A default should be provided by your board, but if not you will need
+	  to use the correct value here.
+
+config DEBUG_UART_CLOCK
+	int "UART input clock"
+	depends on DEBUG_UART
+	help
+	  The UART input clock determines the speed of the internal UART
+	  circuitry. The baud rate is derived from this by dividing the input
+	  clock down.
+
+	  A default should be provided by your board, but if not you will need
+	  to use the correct value here.
 
 config UNIPHIER_SERIAL
 	bool "UniPhier on-chip UART support"
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 4cc00cd2f8..63b0cbf5da 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -8,6 +8,7 @@
 ifdef CONFIG_DM_SERIAL
 obj-y += serial-uclass.o
 obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
+obj-$(CONFIG_PPC) += serial_ppc.o
 else
 obj-y += serial.o
 obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 70c946249f..eb00f1ca8a 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -55,17 +55,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif /* CONFIG_SYS_NS16550_IER */
 
 #ifdef CONFIG_DM_SERIAL
-static void ns16550_writeb(NS16550_t port, int offset, int value)
-{
-	struct ns16550_platdata *plat = port->plat;
-	unsigned char *addr;
 
-	offset *= 1 << plat->reg_shift;
-	addr = map_sysmem(plat->base, 0) + offset;
-	/*
-	 * As far as we know it doesn't make sense to support selection of
-	 * these options at run-time, so use the existing CONFIG options.
-	 */
+static inline void serial_out_shift(unsigned char *addr, int shift, int value)
+{
 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
 	outb(value, (ulong)addr);
 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
@@ -73,19 +65,14 @@ static void ns16550_writeb(NS16550_t port, int offset, int value)
 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
 	out_be32(addr, value);
 #elif defined(CONFIG_SYS_BIG_ENDIAN)
-	writeb(value, addr + (1 << plat->reg_shift) - 1);
+	writeb(value, addr + (1 << shift) - 1);
 #else
 	writeb(value, addr);
 #endif
 }
 
-static int ns16550_readb(NS16550_t port, int offset)
+static inline int serial_in_shift(unsigned char *addr, int shift)
 {
-	struct ns16550_platdata *plat = port->plat;
-	unsigned char *addr;
-
-	offset *= 1 << plat->reg_shift;
-	addr = map_sysmem(plat->base, 0) + offset;
 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
 	return inb((ulong)addr);
 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
@@ -93,12 +80,37 @@ static int ns16550_readb(NS16550_t port, int offset)
 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
 	return in_be32(addr);
 #elif defined(CONFIG_SYS_BIG_ENDIAN)
-	return readb(addr + (1 << plat->reg_shift) - 1);
+	return readb(addr + (1 << reg_shift) - 1);
 #else
 	return readb(addr);
 #endif
 }
 
+static void ns16550_writeb(NS16550_t port, int offset, int value)
+{
+	struct ns16550_platdata *plat = port->plat;
+	unsigned char *addr;
+
+	offset *= 1 << plat->reg_shift;
+	addr = map_sysmem(plat->base, 0) + offset;
+	/*
+	 * As far as we know it doesn't make sense to support selection of
+	 * these options at run-time, so use the existing CONFIG options.
+	 */
+	serial_out_shift(addr, plat->reg_shift, value);
+}
+
+static int ns16550_readb(NS16550_t port, int offset)
+{
+	struct ns16550_platdata *plat = port->plat;
+	unsigned char *addr;
+
+	offset *= 1 << plat->reg_shift;
+	addr = map_sysmem(plat->base, 0) + offset;
+
+	return serial_in_shift(addr, plat->reg_shift);
+}
+
 /* We can clean these up once everything is moved to driver model */
 #define serial_out(value, addr)	\
 	ns16550_writeb(com_port, addr - (unsigned char *)com_port, value)
@@ -106,10 +118,15 @@ static int ns16550_readb(NS16550_t port, int offset)
 	ns16550_readb(com_port, addr - (unsigned char *)com_port)
 #endif
 
-int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
+static inline int calc_divisor(NS16550_t port, int clock, int baudrate)
 {
 	const unsigned int mode_x_div = 16;
 
+	return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
+}
+
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
+{
 #ifdef CONFIG_OMAP1510
 	/* If can't cleanly clock 115200 set div to 1 */
 	if ((clock == 12000000) && (baudrate == 115200)) {
@@ -119,7 +136,7 @@ int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
 	port->osc_12m_sel = 0;			/* clear if previsouly set */
 #endif
 
-	return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
+	return calc_divisor(port, clock, baudrate);
 }
 
 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
@@ -219,6 +236,47 @@ int NS16550_tstc(NS16550_t com_port)
 
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
 
+#ifdef CONFIG_DEBUG_UART_NS16550
+
+#include <debug_uart.h>
+
+void debug_uart_init(void)
+{
+	struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
+	int baud_divisor;
+
+	/*
+	 * We copy the code from above because it is already horribly messy.
+	 * Trying to refactor to nicely remove the duplication doesn't seem
+	 * feasible. The better fix is to move all users of this driver to
+	 * driver model.
+	 */
+	baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
+				    CONFIG_BAUDRATE);
+
+	serial_out_shift(&com_port->ier, 0, CONFIG_SYS_NS16550_IER);
+	serial_out_shift(&com_port->mcr, 0, UART_MCRVAL);
+	serial_out_shift(&com_port->fcr, 0, UART_FCRVAL);
+
+	serial_out_shift(&com_port->lcr, 0, UART_LCR_BKSE | UART_LCRVAL);
+	serial_out_shift(&com_port->dll, 0, baud_divisor & 0xff);
+	serial_out_shift(&com_port->dlm, 0, (baud_divisor >> 8) & 0xff);
+	serial_out_shift(&com_port->lcr, 0, UART_LCRVAL);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+	struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
+
+	while (!(serial_in_shift(&com_port->lsr, 0) & UART_LSR_THRE))
+		;
+	serial_out_shift(&com_port->thr, 0, ch);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
+
 #ifdef CONFIG_DM_SERIAL
 static int ns16550_serial_putc(struct udevice *dev, const char ch)
 {
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index d1b5777cec..3fc7104359 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -258,6 +258,22 @@ static int serial_post_probe(struct udevice *dev)
 #endif
 	int ret;
 
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	if (ops->setbrg)
+		ops->setbrg += gd->reloc_off;
+	if (ops->getc)
+		ops->getc += gd->reloc_off;
+	if (ops->putc)
+		ops->putc += gd->reloc_off;
+	if (ops->pending)
+		ops->pending += gd->reloc_off;
+	if (ops->clear)
+		ops->clear += gd->reloc_off;
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+	if (ops->loop)
+		ops->loop += gd->reloc_off
+#endif
+#endif
 	/* Set the baud rate */
 	if (ops->setbrg) {
 		ret = ops->setbrg(dev, gd->baudrate);
@@ -297,6 +313,7 @@ static int serial_pre_remove(struct udevice *dev)
 UCLASS_DRIVER(serial) = {
 	.id		= UCLASS_SERIAL,
 	.name		= "serial",
+	.flags		= DM_UC_FLAG_SEQ_ALIAS,
 	.post_probe	= serial_post_probe,
 	.pre_remove	= serial_pre_remove,
 	.per_device_auto_alloc_size = sizeof(struct serial_dev_priv),
diff --git a/drivers/serial/serial_ppc.c b/drivers/serial/serial_ppc.c
new file mode 100644
index 0000000000..47141c64eb
--- /dev/null
+++ b/drivers/serial/serial_ppc.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id ppc_serial_ids[] = {
+	{ .compatible = "ns16550" },
+	{ }
+};
+
+static int ppc_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ns16550_platdata *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = ns16550_serial_ofdata_to_platdata(dev);
+	if (ret)
+		return ret;
+	plat->clock = get_serial_clock();
+
+	return 0;
+}
+
+U_BOOT_DRIVER(serial_ns16550) = {
+	.name	= "serial_ppc",
+	.id	= UCLASS_SERIAL,
+	.of_match = ppc_serial_ids,
+	.ofdata_to_platdata = ppc_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.probe = ns16550_serial_probe,
+	.ops	= &ns16550_serial_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 7c1f271376..3641c9f834 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -1,78 +1,21 @@
 /*
  * SuperH SCIF device driver.
  * Copyright (C) 2013  Renesas Electronics Corporation
- * Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
+ * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
  * Copyright (C) 2002 - 2008  Paul Mundt
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <errno.h>
+#include <dm.h>
 #include <asm/io.h>
 #include <asm/processor.h>
-#include "serial_sh.h"
 #include <serial.h>
 #include <linux/compiler.h>
-
-#if defined(CONFIG_CONS_SCIF0)
-# define SCIF_BASE	SCIF0_BASE
-#elif defined(CONFIG_CONS_SCIF1)
-# define SCIF_BASE	SCIF1_BASE
-#elif defined(CONFIG_CONS_SCIF2)
-# define SCIF_BASE	SCIF2_BASE
-#elif defined(CONFIG_CONS_SCIF3)
-# define SCIF_BASE	SCIF3_BASE
-#elif defined(CONFIG_CONS_SCIF4)
-# define SCIF_BASE	SCIF4_BASE
-#elif defined(CONFIG_CONS_SCIF5)
-# define SCIF_BASE	SCIF5_BASE
-#elif defined(CONFIG_CONS_SCIF6)
-# define SCIF_BASE	SCIF6_BASE
-#elif defined(CONFIG_CONS_SCIF7)
-# define SCIF_BASE	SCIF7_BASE
-#else
-# error "Default SCIF doesn't set....."
-#endif
-
-#if defined(CONFIG_SCIF_A)
-	#define SCIF_BASE_PORT	PORT_SCIFA
-#else
-	#define SCIF_BASE_PORT	PORT_SCIF
-#endif
-
-static struct uart_port sh_sci = {
-	.membase	= (unsigned char*)SCIF_BASE,
-	.mapbase	= SCIF_BASE,
-	.type		= SCIF_BASE_PORT,
-};
-
-static void sh_serial_setbrg(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SCIF_USE_EXT_CLK
-	unsigned short dl = DL_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ);
-	sci_out(&sh_sci, DL, dl);
-	/* Need wait: Clock * 1/dl × 1/16 */
-	udelay((1000000 * dl * 16 / CONFIG_SYS_CLK_FREQ) * 1000 + 1);
-#else
-	sci_out(&sh_sci, SCBRR,
-		SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ));
-#endif
-}
-
-static int sh_serial_init(void)
-{
-	sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
-	sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
-	sci_out(&sh_sci, SCSMR, 0);
-	sci_out(&sh_sci, SCSMR, 0);
-	sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
-	sci_in(&sh_sci, SCFCR);
-	sci_out(&sh_sci, SCFCR, 0);
-
-	serial_setbrg();
-	return 0;
-}
+#include <dm/platform_data/serial_sh.h>
+#include "serial_sh.h"
 
 #if defined(CONFIG_CPU_SH7760) || \
 	defined(CONFIG_CPU_SH7780) || \
@@ -86,7 +29,7 @@ static int scif_rxfill(struct uart_port *port)
 static int scif_rxfill(struct uart_port *port)
 {
 	if ((port->mapbase == 0xffe00000) ||
-		(port->mapbase == 0xffe08000)) {
+	    (port->mapbase == 0xffe08000)) {
 		/* SCIF0/1*/
 		return sci_in(port, SCRFDR) & 0xff;
 	} else {
@@ -109,80 +52,253 @@ static int scif_rxfill(struct uart_port *port)
 }
 #endif
 
-static int serial_rx_fifo_level(void)
+static void sh_serial_init_generic(struct uart_port *port)
 {
-	return scif_rxfill(&sh_sci);
+	sci_out(port, SCSCR , SCSCR_INIT(port));
+	sci_out(port, SCSCR , SCSCR_INIT(port));
+	sci_out(port, SCSMR, 0);
+	sci_out(port, SCSMR, 0);
+	sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
+	sci_in(port, SCFCR);
+	sci_out(port, SCFCR, 0);
 }
 
-static void handle_error(void)
+static void
+sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
 {
-	sci_in(&sh_sci, SCxSR);
-	sci_out(&sh_sci, SCxSR, SCxSR_ERROR_CLEAR(&sh_sci));
-	sci_in(&sh_sci, SCLSR);
-	sci_out(&sh_sci, SCLSR, 0x00);
+	if (port->clk_mode == EXT_CLK) {
+		unsigned short dl = DL_VALUE(baudrate, clk);
+		sci_out(port, DL, dl);
+		/* Need wait: Clock * 1/dl × 1/16 */
+		udelay((1000000 * dl * 16 / clk) * 1000 + 1);
+	} else {
+		sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
+	}
 }
 
-static void serial_raw_putc(const char c)
+static void handle_error(struct uart_port *port)
 {
-	while (1) {
-		/* Tx fifo is empty */
-		if (sci_in(&sh_sci, SCxSR) & SCxSR_TEND(&sh_sci))
-			break;
-	}
+	sci_in(port, SCxSR);
+	sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
+	sci_in(port, SCLSR);
+	sci_out(port, SCLSR, 0x00);
+}
+
+static int serial_raw_putc(struct uart_port *port, const char c)
+{
+	/* Tx fifo is empty */
+	if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
+		return -EAGAIN;
 
-	sci_out(&sh_sci, SCxTDR, c);
-	sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci));
+	sci_out(port, SCxTDR, c);
+	sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
+
+	return 0;
 }
 
-static void sh_serial_putc(const char c)
+static int serial_rx_fifo_level(struct uart_port *port)
 {
-	if (c == '\n')
-		serial_raw_putc('\r');
-	serial_raw_putc(c);
+	return scif_rxfill(port);
 }
 
-static int sh_serial_tstc(void)
+static int sh_serial_tstc_generic(struct uart_port *port)
 {
-	if (sci_in(&sh_sci, SCxSR) & SCIF_ERRORS) {
-		handle_error();
+	if (sci_in(port, SCxSR) & SCIF_ERRORS) {
+		handle_error(port);
 		return 0;
 	}
 
-	return serial_rx_fifo_level() ? 1 : 0;
+	return serial_rx_fifo_level(port) ? 1 : 0;
 }
 
-
-static int serial_getc_check(void)
+static int serial_getc_check(struct uart_port *port)
 {
 	unsigned short status;
 
-	status = sci_in(&sh_sci, SCxSR);
+	status = sci_in(port, SCxSR);
 
 	if (status & SCIF_ERRORS)
-		handle_error();
-	if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
-		handle_error();
-	return status & (SCIF_DR | SCxSR_RDxF(&sh_sci));
+		handle_error(port);
+	if (sci_in(port, SCLSR) & SCxSR_ORER(port))
+		handle_error(port);
+	return status & (SCIF_DR | SCxSR_RDxF(port));
 }
 
-static int sh_serial_getc(void)
+static int sh_serial_getc_generic(struct uart_port *port)
 {
 	unsigned short status;
 	char ch;
 
-	while (!serial_getc_check())
-		;
+	if (!serial_getc_check(port))
+		return -EAGAIN;
 
-	ch = sci_in(&sh_sci, SCxRDR);
-	status = sci_in(&sh_sci, SCxSR);
+	ch = sci_in(port, SCxRDR);
+	status = sci_in(port, SCxSR);
 
-	sci_out(&sh_sci, SCxSR, SCxSR_RDxF_CLEAR(&sh_sci));
+	sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 
 	if (status & SCIF_ERRORS)
-			handle_error();
+		handle_error(port);
+
+	if (sci_in(port, SCLSR) & SCxSR_ORER(port))
+		handle_error(port);
+
+	return ch;
+}
+
+#ifdef CONFIG_DM_SERIAL
+
+static int sh_serial_pending(struct udevice *dev, bool input)
+{
+	struct uart_port *priv = dev_get_priv(dev);
+
+	return sh_serial_tstc_generic(priv);
+}
+
+static int sh_serial_putc(struct udevice *dev, const char ch)
+{
+	struct uart_port *priv = dev_get_priv(dev);
+
+	return serial_raw_putc(priv, ch);
+}
+
+static int sh_serial_getc(struct udevice *dev)
+{
+	struct uart_port *priv = dev_get_priv(dev);
+
+	return sh_serial_getc_generic(priv);
+}
+
+static int sh_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct sh_serial_platdata *plat = dev_get_platdata(dev);
+	struct uart_port *priv = dev_get_priv(dev);
+
+	sh_serial_setbrg_generic(priv, plat->clk, baudrate);
+
+	return 0;
+}
+
+static int sh_serial_probe(struct udevice *dev)
+{
+	struct sh_serial_platdata *plat = dev_get_platdata(dev);
+	struct uart_port *priv = dev_get_priv(dev);
+
+	priv->membase	= (unsigned char *)plat->base;
+	priv->mapbase	= plat->base;
+	priv->type	= plat->type;
+	priv->clk_mode	= plat->clk_mode;
+
+	sh_serial_init_generic(priv);
+
+	return 0;
+}
+
+static const struct dm_serial_ops sh_serial_ops = {
+	.putc = sh_serial_putc,
+	.pending = sh_serial_pending,
+	.getc = sh_serial_getc,
+	.setbrg = sh_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_sh) = {
+	.name	= "serial_sh",
+	.id	= UCLASS_SERIAL,
+	.probe	= sh_serial_probe,
+	.ops	= &sh_serial_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+	.priv_auto_alloc_size = sizeof(struct uart_port),
+};
+
+#else /* CONFIG_DM_SERIAL */
+
+#if defined(CONFIG_CONS_SCIF0)
+# define SCIF_BASE	SCIF0_BASE
+#elif defined(CONFIG_CONS_SCIF1)
+# define SCIF_BASE	SCIF1_BASE
+#elif defined(CONFIG_CONS_SCIF2)
+# define SCIF_BASE	SCIF2_BASE
+#elif defined(CONFIG_CONS_SCIF3)
+# define SCIF_BASE	SCIF3_BASE
+#elif defined(CONFIG_CONS_SCIF4)
+# define SCIF_BASE	SCIF4_BASE
+#elif defined(CONFIG_CONS_SCIF5)
+# define SCIF_BASE	SCIF5_BASE
+#elif defined(CONFIG_CONS_SCIF6)
+# define SCIF_BASE	SCIF6_BASE
+#elif defined(CONFIG_CONS_SCIF7)
+# define SCIF_BASE	SCIF7_BASE
+#else
+# error "Default SCIF doesn't set....."
+#endif
+
+#if defined(CONFIG_SCIF_A)
+	#define SCIF_BASE_PORT	PORT_SCIFA
+#else
+	#define SCIF_BASE_PORT	PORT_SCIF
+#endif
+
+static struct uart_port sh_sci = {
+	.membase	= (unsigned char *)SCIF_BASE,
+	.mapbase	= SCIF_BASE,
+	.type		= SCIF_BASE_PORT,
+#ifdef CONFIG_SCIF_USE_EXT_CLK
+	.clk_mode =	EXT_CLK,
+#endif
+};
+
+static void sh_serial_setbrg(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	struct uart_port *port = &sh_sci;
+
+	sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
+}
+
+static int sh_serial_init(void)
+{
+	struct uart_port *port = &sh_sci;
+
+	sh_serial_init_generic(port);
+	serial_setbrg();
+
+	return 0;
+}
+
+static void sh_serial_putc(const char c)
+{
+	struct uart_port *port = &sh_sci;
+
+	if (c == '\n') {
+		while (1) {
+			if  (serial_raw_putc(port, '\r') != -EAGAIN)
+				break;
+		}
+	}
+	while (1) {
+		if  (serial_raw_putc(port, c) != -EAGAIN)
+			break;
+	}
+}
+
+static int sh_serial_tstc(void)
+{
+	struct uart_port *port = &sh_sci;
+
+	return sh_serial_tstc_generic(port);
+}
+
+static int sh_serial_getc(void)
+{
+	struct uart_port *port = &sh_sci;
+	int ch;
+
+	while (1) {
+		ch = sh_serial_getc_generic(port);
+		if (ch != -EAGAIN)
+			break;
+	}
 
-	if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
-		handle_error();
 	return ch;
 }
 
@@ -206,3 +322,4 @@ __weak struct serial_device *default_serial_console(void)
 {
 	return &sh_serial_drv;
 }
+#endif /* CONFIG_DM_SERIAL */
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index ef88c8f273..528aa7351d 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -2,18 +2,16 @@
  * Copy and modify from linux/drivers/serial/sh-sci.h
  */
 
+#include <dm/platform_data/serial_sh.h>
+
 struct uart_port {
 	unsigned long	iobase;		/* in/out[bwl] */
 	unsigned char	*membase;	/* read/write[bwl] */
 	unsigned long	mapbase;	/* for ioremap */
-	unsigned int	type;		/* port type */
+	enum sh_serial_type type;	/* port type */
+	enum sh_clk_mode clk_mode;	/* clock mode */
 };
 
-#define PORT_SCI	52
-#define PORT_SCIF	53
-#define PORT_SCIFA	83
-#define PORT_SCIFB	93
-
 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 #include <asm/regs306x.h>
 #endif
@@ -526,6 +524,7 @@ SCIF_FNS(SCFDR,  0x1c, 16)
 SCIF_FNS(SCxTDR, 0x20,  8)
 SCIF_FNS(SCxRDR, 0x24,  8)
 SCIF_FNS(SCLSR,  0x00,  0)
+SCIF_FNS(DL,	 0x00,  0) /* dummy */
 #elif defined(CONFIG_ARCH_SH7372) || \
 	defined(CONFIG_R8A7740)
 SCIF_FNS(SCSMR,  0x00, 16)
@@ -541,6 +540,7 @@ SCIF_FNS(SCRFDR, 0x3c, 16)
 SCIx_FNS(SCxTDR, 0x20,  8, 0x40,  8)
 SCIx_FNS(SCxRDR, 0x24,  8, 0x60,  8)
 SCIF_FNS(SCLSR,  0x00,  0)
+SCIF_FNS(DL,	 0x00,  0) /* dummy */
 #elif defined(CONFIG_CPU_SH7723) ||\
 	defined(CONFIG_CPU_SH7724)
 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
@@ -555,6 +555,7 @@ SCIF_FNS(SCFER,  0x10, 16)
 SCIF_FNS(SCFCR,  0x18, 16)
 SCIF_FNS(SCFDR,  0x1c, 16)
 SCIF_FNS(SCLSR,  0x24, 16)
+SCIF_FNS(DL,	 0x00,  0) /* dummy */
 #else
 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
@@ -583,18 +584,21 @@ SCIF_FNS(SCRFDR,		     0x0e, 16, 0x20, 16)
 SCIF_FNS(SCSPTR,			0,  0, 0x24, 16)
 SCIF_FNS(SCLSR,				0,  0, 0x28, 16)
 #else
+
 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 #if defined(CONFIG_CPU_SH7722)
 SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 #else
 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 #endif
+SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
+#endif
 #if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 SCIF_FNS(DL,				0,  0, 0x30, 16)
 SCIF_FNS(CKS,				0,  0, 0x34, 16)
-#endif
-SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
+#else
+SCIF_FNS(DL,				0,  0, 0x0,  0) /* dummy */
 #endif
 #endif
 #define sci_in(port, reg) sci_##reg##_in(port)
@@ -725,14 +729,14 @@ static inline int sci_rxd_in(struct uart_port *port)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 #elif defined(CONFIG_CPU_SH7723) ||\
 	defined(CONFIG_CPU_SH7724)
-static inline int scbrr_calc(struct uart_port port, int bps, int clk)
+static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 {
-	if (port.type == PORT_SCIF)
+	if (port->type == PORT_SCIF)
 		return (clk+16*bps)/(32*bps)-1;
 	else
 		return ((clk*2)+16*bps)/(16*bps)-1;
 }
-#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
+#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
@@ -742,3 +746,7 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif
+
+#ifndef DL_VALUE
+#define DL_VALUE(bps, clk) 0
+#endif