sound: Add a driver for max98088

This chip is used by spring. Add a driver for it and update the
samsung_sound driver to pick it up.

Signed-off-by: Simon Glass <sjg@chromium.org>

5 files changed, 633 insertions, 1 deletions

diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
index 22e379681d..bd72dd335e 100644
--- a/drivers/sound/Kconfig
+++ b/drivers/sound/Kconfig
@@ -40,6 +40,14 @@ config I2S_SAMSUNG
 	  option provides an implementation for sound_init() and
 	  sound_play().
 
+config SOUND_MAX98088
+	bool "Support Maxim max98088 audio codec"
+	depends on I2S_SAMSUNG
+	help
+	  Enable the max98088 audio codec. This is connected via I2S for
+	  audio data and I2C for codec control. At present it only works
+	  with the Samsung I2S driver.
+
 config SOUND_MAX98090
 	bool "Support Maxim max98090 audio codec"
 	depends on I2S_SAMSUNG
diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
index d0bf51bab6..170e06ad53 100644
--- a/drivers/sound/Makefile
+++ b/drivers/sound/Makefile
@@ -12,5 +12,6 @@ obj-$(CONFIG_SOUND_SANDBOX)	+= sandbox.o
 obj-$(CONFIG_I2S_ROCKCHIP)	+= rockchip_i2s.o rockchip_sound.o
 obj-$(CONFIG_I2S_SAMSUNG)	+= samsung_sound.o
 obj-$(CONFIG_SOUND_WM8994)	+= wm8994.o
+obj-$(CONFIG_SOUND_MAX98088)	+= max98088.o maxim_codec.o
 obj-$(CONFIG_SOUND_MAX98090)	+= max98090.o maxim_codec.o
 obj-$(CONFIG_SOUND_MAX98095)	+= max98095.o maxim_codec.o
diff --git a/drivers/sound/max98088.c b/drivers/sound/max98088.c
new file mode 100644
index 0000000000..08f0bf861e
--- /dev/null
+++ b/drivers/sound/max98088.c
@@ -0,0 +1,431 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * max98088.c -- MAX98088 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Maxim Integrated Products
+ *
+ * Modified for U-Boot by Chih-Chung Chang (chihchung@chromium.org),
+ * following the changes made in max98095.c
+ */
+
+#include <common.h>
+#include <audio_codec.h>
+#include <div64.h>
+#include <dm.h>
+#include <i2c.h>
+#include <i2s.h>
+#include <sound.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+#include "maxim_codec.h"
+#include "max98088.h"
+
+/* codec mclk clock divider coefficients. Index 0 is reserved. */
+static const int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000,
+				 44100, 48000, 88200, 96000};
+
+/*
+ * codec mclk clock divider coefficients based on sampling rate
+ *
+ * @param rate sampling rate
+ * @param value address of indexvalue to be stored
+ *
+ * @return	0 for success or negative error code.
+ */
+static int rate_value(int rate, u8 *value)
+{
+	int i;
+
+	for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
+		if (rate_table[i] >= rate) {
+			*value = i;
+			return 0;
+		}
+	}
+	*value = 1;
+
+	return -EINVAL;
+}
+
+/*
+ * Sets hw params for max98088
+ *
+ * @priv: max98088 information pointer
+ * @rate: Sampling rate
+ * @bits_per_sample: Bits per sample
+ *
+ * @return -EIO for error, 0 for success.
+ */
+int max98088_hw_params(struct maxim_priv *priv, unsigned int rate,
+		       unsigned int bits_per_sample)
+{
+	int error;
+	u8 regval;
+
+	switch (bits_per_sample) {
+	case 16:
+		error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
+				     M98088_DAI_WS, 0);
+		break;
+	case 24:
+		error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
+				     M98088_DAI_WS, M98088_DAI_WS);
+		break;
+	default:
+		debug("%s: Illegal bits per sample %d.\n",
+		      __func__, bits_per_sample);
+		return -EINVAL;
+	}
+
+	error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, 0);
+
+	if (rate_value(rate, &regval)) {
+		debug("%s: Failed to set sample rate to %d.\n",
+		      __func__, rate);
+		return -EIO;
+	}
+
+	error |= maxim_bic_or(priv, M98088_REG_DAI1_CLKMODE,
+			      M98088_CLKMODE_MASK, regval << 4);
+	priv->rate = rate;
+
+	/* Update sample rate mode */
+	if (rate < 50000)
+		error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
+				      M98088_DAI_DHF, 0);
+	else
+		error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
+				      M98088_DAI_DHF, M98088_DAI_DHF);
+
+	error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN,
+			      M98088_SHDNRUN);
+
+	if (error < 0) {
+		debug("%s: Error setting hardware params.\n", __func__);
+		return -EIO;
+	}
+	priv->rate = rate;
+
+	return 0;
+}
+
+/*
+ * Configures Audio interface system clock for the given frequency
+ *
+ * @priv: max98088 information
+ * @freq: Sampling frequency in Hz
+ *
+ * @return -EIO for error, 0 for success.
+ */
+int max98088_set_sysclk(struct maxim_priv *priv, unsigned int freq)
+{
+	int error = 0;
+	u8 pwr;
+
+	/* Requested clock frequency is already setup */
+	if (freq == priv->sysclk)
+		return 0;
+
+	/*
+	 * Setup clocks for slave mode, and using the PLL
+	 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
+	 *         0x02 (when master clk is 20MHz to 30MHz)..
+	 */
+	if (freq >= 10000000 && freq < 20000000) {
+		error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x10);
+	} else if ((freq >= 20000000) && (freq < 30000000)) {
+		error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x20);
+	} else {
+		debug("%s: Invalid master clock frequency\n", __func__);
+		return -EIO;
+	}
+
+	error |= maxim_i2c_read(priv, M98088_REG_PWR_SYS, &pwr);
+	if (pwr & M98088_SHDNRUN) {
+		error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
+				      M98088_SHDNRUN, 0);
+		error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
+				      M98088_SHDNRUN, M98088_SHDNRUN);
+	}
+
+	debug("%s: Clock at %uHz\n", __func__, freq);
+	if (error < 0)
+		return -EIO;
+
+	priv->sysclk = freq;
+
+	return 0;
+}
+
+/*
+ * Sets Max98090 I2S format
+ *
+ * @priv: max98088 information
+ * @fmt: i2S format - supports a subset of the options defined in i2s.h.
+ *
+ * @return -EIO for error, 0 for success.
+ */
+int max98088_set_fmt(struct maxim_priv *priv, int fmt)
+{
+	u8 reg15val;
+	u8 reg14val = 0;
+	int error = 0;
+
+	if (fmt == priv->fmt)
+		return 0;
+
+	priv->fmt = fmt;
+
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBS_CFS:
+		/* Slave mode PLL */
+		error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_HI,
+					    0x80);
+		error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_LO,
+					    0x00);
+		break;
+	case SND_SOC_DAIFMT_CBM_CFM:
+		/* Set to master mode */
+		reg14val |= M98088_DAI_MAS;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFM:
+	case SND_SOC_DAIFMT_CBM_CFS:
+	default:
+		debug("%s: Clock mode unsupported\n", __func__);
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		reg14val |= M98088_DAI_DLY;
+		break;
+	case SND_SOC_DAIFMT_LEFT_J:
+		break;
+	default:
+		debug("%s: Unrecognized format.\n", __func__);
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		break;
+	case SND_SOC_DAIFMT_NB_IF:
+		reg14val |= M98088_DAI_WCI;
+		break;
+	case SND_SOC_DAIFMT_IB_NF:
+		reg14val |= M98088_DAI_BCI;
+		break;
+	case SND_SOC_DAIFMT_IB_IF:
+		reg14val |= M98088_DAI_BCI | M98088_DAI_WCI;
+		break;
+	default:
+		debug("%s: Unrecognized inversion settings.\n",  __func__);
+		return -EINVAL;
+	}
+
+	error |= maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
+			      M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
+			      M98088_DAI_WCI, reg14val);
+	reg15val = M98088_DAI_BSEL64;
+	error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLOCK, reg15val);
+
+	if (error < 0) {
+		debug("%s: Error setting i2s format.\n", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * max98088_reset() - reset the audio codec
+ *
+ * @priv: max98088 information
+ * @return -EIO for error, 0 for success.
+ */
+static int max98088_reset(struct maxim_priv *priv)
+{
+	int ret, i;
+	u8 val;
+
+	/*
+	 * Reset to hardware default for registers, as there is not a soft
+	 * reset hardware control register.
+	 */
+	for (i = M98088_REG_IRQ_ENABLE; i <= M98088_REG_PWR_SYS; i++) {
+		switch (i) {
+		case M98088_REG_BIAS_CNTL:
+			val = 0xf0;
+			break;
+		case M98088_REG_DAC_BIAS2:
+			val = 0x0f;
+			break;
+		default:
+			val = 0;
+		}
+		ret = maxim_i2c_write(priv, i, val);
+		if (ret < 0) {
+			debug("%s: Failed to reset: %d\n", __func__, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * max98088_device_init() - Initialise max98088 codec device
+ *
+ * @priv: max98088 information
+ *
+ * @return -EIO for error, 0 for success.
+ */
+static int max98088_device_init(struct maxim_priv *priv)
+{
+	unsigned char id;
+	int error = 0;
+
+	/* Enable codec clock */
+	set_xclkout();
+
+	/* reset the codec, the DSP core, and disable all interrupts */
+	error = max98088_reset(priv);
+	if (error != 0) {
+		debug("Reset\n");
+		return error;
+	}
+
+	/* initialize private data */
+	priv->sysclk = -1U;
+	priv->rate = -1U;
+	priv->fmt = -1U;
+
+	error = maxim_i2c_read(priv, M98088_REG_REV_ID, &id);
+	if (error < 0) {
+		debug("%s: Failure reading hardware revision: %d\n",
+		      __func__, id);
+		return -EIO;
+	}
+	debug("%s: Hardware revision: %d\n", __func__, id);
+
+	return 0;
+}
+
+static int max98088_setup_interface(struct maxim_priv *priv)
+{
+	int error;
+
+	/* Reading interrupt status to clear them */
+	error = maxim_i2c_write(priv, M98088_REG_PWR_SYS, M98088_PWRSV);
+	error |= maxim_i2c_write(priv, M98088_REG_IRQ_ENABLE, 0x00);
+
+	/*
+	 * initialize registers to hardware default configuring audio
+	 * interface2 to DAI1
+	 */
+	error |= maxim_i2c_write(priv, M98088_REG_MIX_DAC,
+				 M98088_DAI1L_TO_DACL | M98088_DAI1R_TO_DACR);
+	error |= maxim_i2c_write(priv, M98088_REG_BIAS_CNTL, 0xF0);
+	error |= maxim_i2c_write(priv, M98088_REG_DAC_BIAS2, 0x0F);
+	error |= maxim_i2c_write(priv, M98088_REG_DAI1_IOCFG,
+				 M98088_S2NORMAL | M98088_SDATA);
+
+	/*
+	 * route DACL and DACR output to headphone and speakers
+	 * Ordering: DACL, DACR, DACL, DACR
+	 */
+	error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_LEFT, 1);
+	error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_RIGHT, 1);
+	error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_LEFT, 1);
+	error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_RIGHT, 1);
+
+	/* set volume: -12db */
+	error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_L, 0x0f);
+	error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_R, 0x0f);
+
+	/* set volume: -22db */
+	error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_L, 0x0d);
+	error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_R, 0x0d);
+
+	/* power enable */
+	error |= maxim_i2c_write(priv, M98088_REG_PWR_EN_OUT,
+				 M98088_HPLEN | M98088_HPREN | M98088_SPLEN |
+				 M98088_SPREN | M98088_DALEN | M98088_DAREN);
+	if (error < 0)
+		return -EIO;
+
+	return 0;
+}
+
+static int max98088_do_init(struct maxim_priv *priv, int sampling_rate,
+			    int mclk_freq, int bits_per_sample)
+{
+	int ret = 0;
+
+	ret = max98088_setup_interface(priv);
+	if (ret < 0) {
+		debug("%s: max98088 setup interface failed\n", __func__);
+		return ret;
+	}
+
+	ret = max98088_set_sysclk(priv, mclk_freq);
+	if (ret < 0) {
+		debug("%s: max98088 codec set sys clock failed\n", __func__);
+		return ret;
+	}
+
+	ret = max98088_hw_params(priv, sampling_rate, bits_per_sample);
+
+	if (ret == 0) {
+		ret = max98088_set_fmt(priv, SND_SOC_DAIFMT_I2S |
+				       SND_SOC_DAIFMT_NB_NF |
+				       SND_SOC_DAIFMT_CBS_CFS);
+	}
+
+	return ret;
+}
+
+static int max98088_set_params(struct udevice *dev, int interface, int rate,
+			       int mclk_freq, int bits_per_sample,
+			       uint channels)
+{
+	struct maxim_priv *priv = dev_get_priv(dev);
+
+	return max98088_do_init(priv, rate, mclk_freq, bits_per_sample);
+}
+
+static int max98088_probe(struct udevice *dev)
+{
+	struct maxim_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->dev = dev;
+	ret = max98088_device_init(priv);
+	if (ret < 0) {
+		debug("%s: max98088 codec chip init failed\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct audio_codec_ops max98088_ops = {
+	.set_params	= max98088_set_params,
+};
+
+static const struct udevice_id max98088_ids[] = {
+	{ .compatible = "maxim,max98088" },
+	{ }
+};
+
+U_BOOT_DRIVER(max98088) = {
+	.name		= "max98088",
+	.id		= UCLASS_AUDIO_CODEC,
+	.of_match	= max98088_ids,
+	.probe		= max98088_probe,
+	.ops		= &max98088_ops,
+	.priv_auto_alloc_size	= sizeof(struct maxim_priv),
+};
diff --git a/drivers/sound/max98088.h b/drivers/sound/max98088.h
new file mode 100644
index 0000000000..127d2bda30
--- /dev/null
+++ b/drivers/sound/max98088.h
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * max98088.h -- MAX98088 ALSA SoC Audio driver
+ *
+ * Copyright 2010 Maxim Integrated Products
+ */
+
+#ifndef _MAX98088_H
+#define _MAX98088_H
+
+/* MAX98088 Registers Definition */
+#define M98088_REG_IRQ_STATUS		0x00
+#define M98088_REG_MIC_STATUS		0x01
+#define M98088_REG_JACK_STAUS		0x02
+#define M98088_REG_BATTERY_VOLTAGE	0x03
+#define M98088_REG_IRQ_ENABLE		0x0f
+#define M98088_REG_SYS_CLK		0X10
+#define M98088_REG_DAI1_CLKMODE		0x11
+#define M98088_REG_DAI1_CLKCFG_HI	0x12
+#define M98088_REG_DAI1_CLKCFG_LO	0x13
+#define M98088_REG_DAI1_FORMAT		0x14
+#define M98088_REG_DAI1_CLOCK		0x15
+#define M98088_REG_DAI1_IOCFG		0x16
+#define M98088_REG_DAI1_TDM		0X17
+#define M98088_REG_DAI1_FILTERS		0x18
+#define M98088_REG_DAI2_CLKMODE		0x19
+#define M98088_REG_DAI2_CLKCFG_HI	0x1a
+#define M98088_REG_DAI2_CLKCFG_LO	0x1b
+#define M98088_REG_DAI2_FORMAT		0x1c
+#define M98088_REG_DAI2_CLOCK		0x1d
+#define M98088_REG_DAI2_IOCFG		0x1e
+#define M98088_REG_DAI2_TDM		0X1f
+#define M98088_REG_DAI2_FILTERS		0x20
+#define M98088_REG_SRC			0X21
+#define M98088_REG_MIX_DAC		0X22
+#define M98088_REG_MIX_ADC_LEFT		0x23
+#define M98088_REG_MIX_ADC_RIGHT	0x24
+#define M98088_REG_MIX_HP_LEFT		0x25
+#define M98088_REG_MIX_HP_RIGHT		0x26
+#define M98088_REG_MIX_HP_CNTL		0x27
+#define M98088_REG_MIX_REC_LEFT		0x28
+#define M98088_REG_MIX_REC_RIGHT	0x29
+#define M98088_REG_MIC_REC_CNTL		0x2a
+#define M98088_REG_MIX_SPK_LEFT		0x2b
+#define M98088_REG_MIX_SPK_RIGHT	0x2c
+#define M98088_REG_MIX_SPK_CNTL		0x2d
+#define M98088_REG_LVL_SIDETONE		0x2e
+#define M98088_REG_LVL_DAI1_PLAY	0x2f
+#define M98088_REG_LVL_DAI1_PLAY_EQ	0x30
+#define M98088_REG_LVL_DAI2_PLAY	0x31
+#define M98088_REG_LVL_DAI2_PLAY_EQ	0x32
+#define M98088_REG_LVL_ADC_L		0X33
+#define M98088_REG_LVL_ADC_R		0X34
+#define M98088_REG_LVL_MIC1		0X35
+#define M98088_REG_LVL_MIC2		0X36
+#define M98088_REG_LVL_INA		0X37
+#define M98088_REG_LVL_INB		0X38
+#define M98088_REG_LVL_HP_L		0X39
+#define M98088_REG_LVL_HP_R		0X3a
+#define M98088_REG_LVL_REC_L		0X3b
+#define M98088_REG_LVL_REC_R		0X3c
+#define M98088_REG_LVL_SPK_L		0X3d
+#define M98088_REG_LVL_SPK_R		0X3e
+#define M98088_REG_MICAGC_CFG		0x3f
+#define M98088_REG_MICAGC_THRESH	0x40
+#define M98088_REG_SPKDHP		0X41
+#define M98088_REG_SPKDHP_THRESH	0x42
+#define M98088_REG_SPKALC_COMP		0x43
+#define M98088_REG_PWRLMT_CFG		0x44
+#define M98088_REG_PWRLMT_TIME		0x45
+#define M98088_REG_THDLMT_CFG		0x46
+#define M98088_REG_CFG_AUDIO_IN		0x47
+#define M98088_REG_CFG_MIC		0X48
+#define M98088_REG_CFG_LEVEL		0X49
+#define M98088_REG_CFG_BYPASS		0x4a
+#define M98088_REG_CFG_JACKDET		0x4b
+#define M98088_REG_PWR_EN_IN		0X4c
+#define M98088_REG_PWR_EN_OUT		0x4d
+#define M98088_REG_BIAS_CNTL		0X4e
+#define M98088_REG_DAC_BIAS1		0X4f
+#define M98088_REG_DAC_BIAS2		0X50
+#define M98088_REG_PWR_SYS		0X51
+#define M98088_REG_DAI1_EQ_BASE		0x52
+#define M98088_REG_DAI2_EQ_BASE		0x84
+#define M98088_REG_DAI1_BIQUAD_BASE	0xb6
+#define M98088_REG_DAI2_BIQUAD_BASE	0xc0
+#define M98088_REG_REV_ID		0xff
+
+#define M98088_REG_CNT			(0xff + 1)
+
+/* MAX98088 Registers Bit Fields */
+
+/* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */
+#define M98088_CLKMODE_MASK		0xFF
+
+/* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */
+#define M98088_DAI_MAS			BIT(7)
+#define M98088_DAI_WCI			BIT(6)
+#define M98088_DAI_BCI			BIT(5)
+#define M98088_DAI_DLY			BIT(4)
+#define M98088_DAI_TDM			BIT(2)
+#define M98088_DAI_FSW			BIT(1)
+#define M98088_DAI_WS			BIT(0)
+
+/* M98088_REG_15_DAI1_CLOCK, M98088_REG_1D_DAI2_CLOCK */
+#define M98088_DAI_BSEL64		BIT(0)
+#define M98088_DAI_OSR64		BIT(6)
+
+/* M98088_REG_16_DAI1_IOCFG, M98088_REG_1E_DAI2_IOCFG */
+#define M98088_S1NORMAL			BIT(6)
+#define M98088_S2NORMAL			(2 << 6)
+#define M98088_SDATA			(3 << 0)
+
+/* M98088_REG_18_DAI1_FILTERS, M98088_REG_20_DAI2_FILTERS */
+#define M98088_DAI_DHF			BIT(3)
+
+/* M98088_REG_22_MIX_DAC */
+#define M98088_DAI1L_TO_DACL		BIT(7)
+#define M98088_DAI1R_TO_DACL		BIT(6)
+#define M98088_DAI2L_TO_DACL		BIT(5)
+#define M98088_DAI2R_TO_DACL		BIT(4)
+#define M98088_DAI1L_TO_DACR		BIT(3)
+#define M98088_DAI1R_TO_DACR		BIT(2)
+#define M98088_DAI2L_TO_DACR		BIT(1)
+#define M98088_DAI2R_TO_DACR		BIT(0)
+
+/* M98088_REG_2A_MIC_REC_CNTL */
+#define M98088_REC_LINEMODE		BIT(7)
+#define M98088_REC_LINEMODE_MASK	BIT(7)
+
+/* M98088_REG_2D_MIX_SPK_CNTL */
+#define M98088_MIX_SPKR_GAIN_MASK       (3 << 2)
+#define M98088_MIX_SPKR_GAIN_SHIFT      2
+#define M98088_MIX_SPKL_GAIN_MASK       (3 << 0)
+#define M98088_MIX_SPKL_GAIN_SHIFT      0
+
+/* M98088_REG_2F_LVL_DAI1_PLAY, M98088_REG_31_LVL_DAI2_PLAY */
+#define M98088_DAI_MUTE			BIT(7)
+#define M98088_DAI_MUTE_MASK		BIT(7)
+#define M98088_DAI_VOICE_GAIN_MASK      (3 << 4)
+#define M98088_DAI_ATTENUATION_MASK     (0xf << 0)
+#define M98088_DAI_ATTENUATION_SHIFT    0
+
+/* M98088_REG_35_LVL_MIC1, M98088_REG_36_LVL_MIC2 */
+#define M98088_MICPRE_MASK		(3 << 5)
+#define M98088_MICPRE_SHIFT		5
+
+/* M98088_REG_3A_LVL_HP_R */
+#define M98088_HP_MUTE			BIT(7)
+
+/* M98088_REG_3C_LVL_REC_R */
+#define M98088_REC_MUTE			BIT(7)
+
+/* M98088_REG_3E_LVL_SPK_R */
+#define M98088_SP_MUTE			BIT(7)
+
+/* M98088_REG_48_CFG_MIC */
+#define M98088_EXTMIC_MASK		(3 << 0)
+#define M98088_DIGMIC_L			BIT(5)
+#define M98088_DIGMIC_R			BIT(4)
+
+/* M98088_REG_49_CFG_LEVEL */
+#define M98088_VSEN			BIT(6)
+#define M98088_ZDEN			BIT(5)
+#define M98088_EQ2EN			BIT(1)
+#define M98088_EQ1EN			BIT(0)
+
+/* M98088_REG_4C_PWR_EN_IN */
+#define M98088_INAEN			BIT(7)
+#define M98088_INBEN			BIT(6)
+#define M98088_MBEN			BIT(3)
+#define M98088_ADLEN			BIT(1)
+#define M98088_ADREN			BIT(0)
+
+/* M98088_REG_4D_PWR_EN_OUT */
+#define M98088_HPLEN			BIT(7)
+#define M98088_HPREN			BIT(6)
+#define M98088_HPEN			(BIT(7) | BIT(6))
+#define M98088_SPLEN			BIT(5)
+#define M98088_SPREN			BIT(4)
+#define M98088_RECEN			BIT(3)
+#define M98088_DALEN			BIT(1)
+#define M98088_DAREN			BIT(0)
+
+/* M98088_REG_51_PWR_SYS */
+#define M98088_SHDNRUN			BIT(7)
+#define M98088_PERFMODE			BIT(3)
+#define M98088_HPPLYBACK		BIT(2)
+#define M98088_PWRSV8K			BIT(1)
+#define M98088_PWRSV			BIT(0)
+
+#endif
diff --git a/drivers/sound/samsung_sound.c b/drivers/sound/samsung_sound.c
index 1d711c8732..84064ebd0f 100644
--- a/drivers/sound/samsung_sound.c
+++ b/drivers/sound/samsung_sound.c
@@ -89,7 +89,7 @@ static const struct sound_ops samsung_sound_ops = {
 
 static const struct udevice_id samsung_sound_ids[] = {
 	{ .compatible = "google,snow-audio-max98095" },
-	{ .compatible = "google,spring-audio-max98095" },
+	{ .compatible = "google,spring-audio-max98088" },
 	{ .compatible = "samsung,smdk5420-audio-wm8994" },
 	{ .compatible = "google,peach-audio-max98090" },
 	{ }