diff options
| author | Vignesh Raghavendra <vigneshr@ti.com> | 2020-01-27 10:36:40 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2020-01-27 22:27:22 +0530 |
| commit | ffab212123481aa44f37cd4fdb4476ec15ff98b6 (patch) | |
| tree | cc80bd2eb97b2d4a241c9f6e42b6299c6c0b905c /drivers/spi/cadence_qspi.h | |
| parent | d640772021589214bd7606d481ae1f52fbe62fe6 (diff) | |
spi: cadence-qspi: Add direct mode support
Add support for Direct Access Controller mode of Cadence QSPI. This
allows MMIO access to SPI NOR flash providing better read performance.
Direct mode is only exercised if AHB window size is greater than 8MB.
Support for flash address remapping is also not supported at the moment
and can be added in future.
For better performance, driver uses DMA to copy data from flash in
direct mode using dma_memcpy().
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/spi/cadence_qspi.h')
| -rw-r--r-- | drivers/spi/cadence_qspi.h | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index d66201ec92..ae459c74a1 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -24,6 +24,8 @@ struct cadence_spi_platdata { u32 fifo_depth; u32 fifo_width; u32 trigger_address; + fdt_addr_t ahbsize; + bool use_dac_mode; /* Flash parameters */ u32 page_size; @@ -53,20 +55,21 @@ struct cadence_spi_priv { void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat); void cadence_qspi_apb_controller_enable(void *reg_base_addr); void cadence_qspi_apb_controller_disable(void *reg_base_addr); +void cadence_qspi_apb_dac_mode_enable(void *reg_base); int cadence_qspi_apb_command_read(void *reg_base_addr, const struct spi_mem_op *op); int cadence_qspi_apb_command_write(void *reg_base_addr, const struct spi_mem_op *op); -int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, - const struct spi_mem_op *op); -int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, - unsigned int rxlen, u8 *rxbuf); -int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, - const struct spi_mem_op *op); -int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, - unsigned int txlen, const u8 *txbuf); +int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat, + const struct spi_mem_op *op); void cadence_qspi_apb_chipselect(void *reg_base, unsigned int chip_select, unsigned int decoder_enable); |