diff options
| author | Phil Edworthy <PHIL.EDWORTHY@renesas.com> | 2016-11-29 12:58:26 +0000 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2016-12-15 16:57:27 +0100 |
| commit | cc80a897e4fafbd9e9b6920eb866f0600a5cd5ee (patch) | |
| tree | 6318e50e26090b158cc1afa56bcafd05c716a743 /drivers/spi/cadence_qspi_apb.c | |
| parent | 1b7c28f5147144d7902d048ca90be58987899c25 (diff) | |
spi: cadence_qspi: Fix clearing of pol/pha bits
Or'ing together bit positions is clearly wrong.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers/spi/cadence_qspi_apb.c')
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e285d3c1e7..2403e717dc 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -311,8 +311,8 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base, cadence_qspi_apb_controller_disable(reg_base); reg = readl(reg_base + CQSPI_REG_CONFIG); - reg &= ~(1 << - (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); + reg &= ~(1 << CQSPI_REG_CONFIG_CLK_POL_LSB); + reg &= ~(1 << CQSPI_REG_CONFIG_CLK_PHA_LSB); reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); |