diff options
| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-10-09 14:14:07 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-12-19 15:23:01 +0100 |
| commit | bea91b0c9b45420fd2a4a1bb1567c90518d09d9e (patch) | |
| tree | 023e1123487d85a7fb2a42d9cc8d861b0c74c93c /drivers/spi/designware_spi.c | |
| parent | 9766a9c65322402b3f0af7aa1f7d258d18dab9d1 (diff) | |
DW SPI: Allow to overload the management of the external CS
On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..
By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'drivers/spi/designware_spi.c')
| -rw-r--r-- | drivers/spi/designware_spi.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 5cca414486..02d93763d4 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -369,7 +369,13 @@ static int poll_transfer(struct dw_spi_priv *priv) return 0; } -static void external_cs_manage(struct udevice *dev, bool on) +/* + * We define external_cs_manage function as 'weak' as some targets + * (like MSCC Ocelot) don't control the external CS pin using a GPIO + * controller. These SoCs use specific registers to control by + * software the SPI pins (and especially the CS). + */ +__weak void external_cs_manage(struct udevice *dev, bool on) { #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) struct dw_spi_priv *priv = dev_get_priv(dev->parent); |