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authorPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2019-02-03 16:17:32 +0100
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2019-05-01 00:00:04 +0200
commit51a644a1b84272ef49ffc8affe5599ef645a98fe (patch)
tree368988c271ba4cea9b02ab374157c8c9a7d66c34 /drivers/spi/mxc_spi.c
parent8aa6c921f739f818cc1137b45a4bdca865745f37 (diff)
rockchip: spi: add driver-data and a 'rxonly_manages_fifo' flag
The SPI controller's documentation (I only had access to the RK3399, RK3368 and PX30 TRMs) specifies that, when operating in master-mode, the controller will stop the SCLK to avoid RXFIFO overruns and TXFIFO underruns. Looks like my worries that we'd need to support DMA-330 (aka PL330) to make any further progress were unfounded. This adds a driver-data structure to capture hardware-specific settings of individual controller instances (after all, we don't know if all versions are well-behaved) and adds a 'master_manages_fifo' flag to it. The first use of said flag is in the optimised receive-only transfer-handler, which can now request 64Kframe (i.e. 128KByte) bursts of data on each reprogramming of CTRLR1 (i.e. every time through the loop). This improves throughput to 46.85MBit/s (a 94.65% bus-utilisation). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'drivers/spi/mxc_spi.c')
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