diff options
author | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
commit | c1b62ba9ca0e41fdd548cb3bb9af3b3f90d4a393 (patch) | |
tree | 7e653a1823011bfb075540428bfdab96707f1517 /drivers/spi/rk_spi.c | |
parent | bc5d0384458466ed5b3608d326eec03cd4f13016 (diff) | |
parent | 217273cd441fe3d00a1bdad143dcb656854963f9 (diff) |
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'drivers/spi/rk_spi.c')
-rw-r--r-- | drivers/spi/rk_spi.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 7921ea0d75..c70d636277 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -210,6 +210,14 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) static int rockchip_spi_calc_modclk(ulong max_freq) { + /* + * While this is not strictly correct for the RK3368, as the + * GPLL will be 576MHz, things will still work, as the + * clk_set_rate(...) implementation in our clock-driver will + * chose the next closest rate not exceeding what we request + * based on the output of this function. + */ + unsigned div; const unsigned long gpll_hz = 594000000UL; @@ -443,6 +451,7 @@ static const struct dm_spi_ops rockchip_spi_ops = { static const struct udevice_id rockchip_spi_ids[] = { { .compatible = "rockchip,rk3288-spi" }, + { .compatible = "rockchip,rk3368-spi" }, { .compatible = "rockchip,rk3399-spi" }, { } }; |