diff options
| author | Ye Li <ye.li@nxp.com> | 2019-08-14 11:31:27 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-10-08 16:36:37 +0200 |
| commit | 7949576664ac8fe8c0da08fcd8c611b9616719f1 (patch) | |
| tree | 1a647c71940659471cf3916c4be70fffe6bf0544 /drivers/spi/spi-mem-nodm.c | |
| parent | 4ee0ff1268d3302a83da97af2a61869f672be473 (diff) | |
spi: fsl_qspi: Fix DDR mode setting for latest iMX platforms
On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller
is updated to have TDH field in FLSHCR register. According to reference
manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX
DDR delay logic won't be enabled.
Another issue in DDR mode is the MCR register will be overwritten in
every read/write/erase operation. This causes DDR_EN been cleared while
TDH=1, then no clk2x output for TX data shift and all operations will
fail.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'drivers/spi/spi-mem-nodm.c')
0 files changed, 0 insertions, 0 deletions