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| author | Michal Simek <michal.simek@xilinx.com> | 2015-09-08 17:20:01 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2016-01-27 15:55:54 +0100 |
| commit | f17ea71d3a8c44c9a74ab1df1eca43b9755cb225 (patch) | |
| tree | 6564b5c2ee3a91ef81910c3be092ab1b2119ad16 /drivers/spi/zynq_spi.c | |
| parent | 0179063273484ba2a869e30d36383044dfcf4087 (diff) | |
net: zynq: Change MDC setup for arm64
MDC setting depends on pclk input clocks which varies across SoC. This
driver is used by xilinx zynq and zynqmp SOC.
Input clock frequence on silicon is 125MHz where divider 64 put
frequency below 2.5MHz requires by spec (125/64=1.95).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/spi/zynq_spi.c')
0 files changed, 0 insertions, 0 deletions