diff options
| author | Phil Edworthy <PHIL.EDWORTHY@renesas.com> | 2016-11-29 12:58:28 +0000 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2016-12-15 16:57:27 +0100 |
| commit | 0ceb4d9e9a64dcc662ea52150feebed37deda716 (patch) | |
| tree | f80445230d3349542a42b5c7807e17dea8c46a48 /drivers/spi | |
| parent | 32068c42a7230ad1ef756ed7a201cc3b3c580076 (diff) | |
spi: cadence_qspi: Better debug information on the SPI clock rate
Show what the output clock rate actually is.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index b5c664fe36..0a2963de35 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -280,13 +280,13 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base, */ div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1; - debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__, - ref_clk_hz, sclk_hz, div); - /* ensure the baud rate doesn't exceed the max value */ if (div > CQSPI_REG_CONFIG_BAUD_MASK) div = CQSPI_REG_CONFIG_BAUD_MASK; + debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__, + ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1))); + reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB); writel(reg, reg_base + CQSPI_REG_CONFIG); |