diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2019-09-25 17:45:25 +0800 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-10-25 17:20:44 +0200 |
| commit | 43405e009be86436affdf355f1e0549bdb6c9b9b (patch) | |
| tree | ce8879707b9d209faa9aa83641eb41d4b3756293 /drivers/spi | |
| parent | 54a6b8e793dd8baf1621cd0c5d6eeeaa542bb329 (diff) | |
spi: mt7621-spi: restore default register value after each xfer
Currently this driver uses a different way to implement the spi xfer,
by modifying some fields of two registers, which is incompatible with the
MTK's original SDK linux driver. This will cause the flash data being
damaged by the SDK driver.
This patch lets the mt7621_spi_set_cs() restore the original register
fields after cs deactivated.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/mt7621_spi.c | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c index 716256ab59..90e85c6b44 100644 --- a/drivers/spi/mt7621_spi.c +++ b/drivers/spi/mt7621_spi.c @@ -21,6 +21,10 @@ #define MT7621_SPI_TRANS 0x00 #define MT7621_SPI_TRANS_START BIT(8) #define MT7621_SPI_TRANS_BUSY BIT(16) +#define TRANS_ADDR_SZ GENMASK(20, 19) +#define TRANS_ADDR_SZ_SHIFT 19 +#define TRANS_MOSI_BCNT GENMASK(3, 0) +#define TRANS_MOSI_BCNT_SHIFT 0 #define MT7621_SPI_OPCODE 0x04 #define MT7621_SPI_DATA0 0x08 @@ -50,20 +54,22 @@ struct mt7621_spi { unsigned int sys_freq; }; -static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) -{ - setbits_le32(rs->base + MT7621_SPI_MASTER, - MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); -} - static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable) { - u32 val = 0; - debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable"); - if (enable) - val = BIT(cs); - iowrite32(val, rs->base + MT7621_SPI_POLAR); + + if (enable) { + setbits_le32(rs->base + MT7621_SPI_MASTER, + MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); + iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR); + } else { + iowrite32(0, rs->base + MT7621_SPI_POLAR); + iowrite32((2 << TRANS_ADDR_SZ_SHIFT) | + (1 << TRANS_MOSI_BCNT_SHIFT), + rs->base + MT7621_SPI_TRANS); + clrbits_le32(rs->base + MT7621_SPI_MASTER, + MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); + } } static int mt7621_spi_set_mode(struct udevice *bus, uint mode) @@ -273,8 +279,6 @@ static int mt7621_spi_probe(struct udevice *dev) return -EINVAL; } - mt7621_spi_reset(rs, 0); - return 0; } |