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authorKuo-Jung Su <dantesu@faraday-tech.com>2013-12-20 12:32:59 +0800
committerMarek Vasut <marex@denx.de>2014-01-13 12:15:12 +0100
commitbd5e301d35621f2b00e0ecd77464c6c0e967fdbb (patch)
treef99f8029a9ea646ebd387377902dc4a4339c5a5e /drivers/usb/gadget/fotg210.c
parent7f673c99c2d8d1aa21996c5b914f06d784b080ca (diff)
usb: gadget: fotg210: add w1c interrupt status support
Since hardware revision 1.11.0, the following interrupt status registers are now W1C (i.e., write 1 clear): 1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5) 2. Interrupt Source Group 2 Register (0x14C) (All bits) And before revision 1.11.0, these registers are all R/W. Which means software must write a 0 to clear the status. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/usb/gadget/fotg210.c')
-rw-r--r--drivers/usb/gadget/fotg210.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c
index 6e19db15fa..cc5c507f87 100644
--- a/drivers/usb/gadget/fotg210.c
+++ b/drivers/usb/gadget/fotg210.c
@@ -847,6 +847,13 @@ int usb_gadget_handle_interrupts(void)
/* CX interrupts */
if (gisr & GISR_GRP0) {
st = readl(&regs->gisr0);
+ /*
+ * Write 1 and then 0 works for both W1C & RW.
+ *
+ * HW v1.11.0+: It's a W1C register (write 1 clear)
+ * HW v1.10.0-: It's a R/W register (write 0 clear)
+ */
+ writel(st & GISR0_CXABORT, &regs->gisr0);
writel(0, &regs->gisr0);
if (st & GISR0_CXERR)
@@ -873,6 +880,13 @@ int usb_gadget_handle_interrupts(void)
/* Device Status Interrupts */
if (gisr & GISR_GRP2) {
st = readl(&regs->gisr2);
+ /*
+ * Write 1 and then 0 works for both W1C & RW.
+ *
+ * HW v1.11.0+: It's a W1C register (write 1 clear)
+ * HW v1.10.0-: It's a R/W register (write 0 clear)
+ */
+ writel(st, &regs->gisr2);
writel(0, &regs->gisr2);
if (st & GISR2_RESET)