summaryrefslogtreecommitdiff
path: root/drivers/usb/host
diff options
context:
space:
mode:
authorSriram Dash <sriram.dash@nxp.com>2016-09-23 12:57:52 +0530
committerMarek Vasut <marex@denx.de>2016-09-27 23:30:49 +0200
commit4c043712e9910ef1d612aedbd8304a1f7348ef5f (patch)
tree555b48572b27ad36a9585b6078aa33cc16b0dde1 /drivers/usb/host
parentc609775e6fe6ce70d8ad3e244440b42fbf66bc13 (diff)
drivers: usb: xhci-fsl: Implement Erratum A-010151 for FSL USB3 controller
Currently the controller by default enables the Receive Detect feature in P3 mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive detection in P3 mode. Enabling the USB3 controller to configure USB in P2 mode whenever the Receive Detect feature is required. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Diffstat (limited to 'drivers/usb/host')
-rw-r--r--drivers/usb/host/xhci-fsl.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 2529d0eb13..798c358fd9 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -84,6 +84,19 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
/* Change beat burst and outstanding pipelined transfers requests */
fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
+ /*
+ * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
+ * reliably support Rx Detect in P3 mode(P3 is the default
+ * setting). Therefore, some USB3.0 devices may not be detected
+ * reliably in Super Speed mode. So, USB controller to configure
+ * USB in P2 mode whenever the Receive Detect feature is required.
+ * whenever the Receive Detect feature is required.
+ */
+ if (has_erratum_a010151())
+ clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
+ DWC3_GUSB3PIPECTL_DISRXDETP3,
+ DWC3_GUSB3PIPECTL_DISRXDETP3);
+
return ret;
}