diff options
| author | Tom Rini <trini@konsulko.com> | 2016-07-28 08:45:00 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-07-28 08:45:00 -0400 |
| commit | 4711e7f7af839b41a6d78490257a9e7975494dd3 (patch) | |
| tree | 7fb01e8da7cee537ebd1a070c750da7c4cc43482 /drivers/usb | |
| parent | fe34b6a4845476208ca7d19a35179e56bebf3877 (diff) | |
| parent | 77cbd3a14184c61d55d7fcddd88fa4e96efc9901 (diff) | |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'drivers/usb')
| -rw-r--r-- | drivers/usb/host/Kconfig | 16 | ||||
| -rw-r--r-- | drivers/usb/host/ehci-mx6.c | 14 |
2 files changed, 25 insertions, 5 deletions
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 5092251ee0..7f94c1f372 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -74,6 +74,22 @@ config USB_EHCI_MX6 ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. +config USB_EHCI_MX7 + bool "Support for i.MX7 on-chip EHCI USB controller" + depends on ARCH_MX7 + default y + ---help--- + Enables support for the on-chip EHCI controller on i.MX7 SoCs. + +if USB_EHCI_MX7 + +config MXC_USB_OTG_HACTIVE + bool "USB Power pin high active" + ---help--- + Set the USB Power pin polarity to be high active (PWR_POL) + +endif + config USB_EHCI_MSM bool "Support for Qualcomm on-chip EHCI USB controller" depends on DM_USB diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 069f116ed2..8352c2bfc5 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -49,7 +49,7 @@ #define USBNC_OFFSET 0x200 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ -#define UCTRL_PM (1 << 9) /* OTG Power Mask */ +#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */ #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ @@ -207,12 +207,20 @@ static void usb_power_config(int index) struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + (0x10000 * index) + USBNC_OFFSET); void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); /* * Clear the ACAENB to enable usb_otg_id detection, * otherwise it is the ACA detection enabled. */ clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); + + /* Set power polarity to high active */ +#ifdef CONFIG_MXC_USB_OTG_HACTIVE + setbits_le32(ctrl, UCTRL_PWR_POL); +#else + clrbits_le32(ctrl, UCTRL_PWR_POL); +#endif } int usb_phy_mode(int port) @@ -250,11 +258,7 @@ static void usb_oc_config(int index) setbits_le32(ctrl, UCTRL_OVER_CUR_POL); #endif -#if defined(CONFIG_MX6) setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); -#elif defined(CONFIG_MX7) - setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM); -#endif } /** |