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authorDan Murphy <dmurphy@ti.com>2013-08-01 14:05:57 -0500
committerMarek Vasut <marex@denx.de>2013-08-26 21:55:46 +0200
commitd3d037ae18c33a16e49630ce2adbc9fea1a680eb (patch)
tree84148840eeb5fbd5e146fc37eaa99d95e1ccfaa0 /drivers/usb
parent5a7bd38437b3fb170cea3b576975f4e4f929299a (diff)
ARM: OMAP5: USB: Add OMAP5 common USB EHCI information
* Enable the OMAP5 EHCI host clocks * Add OMAP5 EHCI register definitions * Add OMAP5 ES2 host revision Signed-off-by: Dan Murphy <dmurphy@ti.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/host/ehci-omap.c26
1 files changed, 24 insertions, 2 deletions
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index 032d5e5ec2..ec24fe05a3 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -96,7 +96,8 @@ inline int __board_usb_init(void)
int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
- defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
+ defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
+ defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
/* controls PHY(s) reset signal(s) */
static inline void omap_ehci_phy_reset(int on, int delay)
{
@@ -115,6 +116,10 @@ static inline void omap_ehci_phy_reset(int on, int delay)
gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
#endif
+#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
+ gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
+#endif
/* Hold the PHY in RESET for enough time till DIR is high */
/* Refer: ISSUE1 */
@@ -198,10 +203,27 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
else
setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
} else if (rev == OMAP_USBHS_REV2) {
+
clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
- /* Clear port mode fields for PHY mode*/
+ /* Clear port mode fields for PHY mode */
+
+ if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
+ setbits_le32(&reg, OMAP_P1_MODE_HSIC);
+
+ if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
+ setbits_le32(&reg, OMAP_P2_MODE_HSIC);
+
+ } else if (rev == OMAP_USBHS_REV2_1) {
+
+ clrsetbits_le32(&reg,
+ (OMAP_P1_MODE_CLEAR |
+ OMAP_P2_MODE_CLEAR |
+ OMAP_P3_MODE_CLEAR),
+ OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
+
+ /* Clear port mode fields for PHY mode */
if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
setbits_le32(&reg, OMAP_P1_MODE_HSIC);