diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2014-02-28 15:12:25 +0800 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2014-08-11 17:31:41 +0200 |
| commit | e66866c542e492c42f04cfc2e59317203b7cd6ea (patch) | |
| tree | 7b9f9ab94172bb0eb046029f7b4bd821ba0f0f91 /drivers/video/ipu.h | |
| parent | 3c5fabd13993172e6c29500cc78de8ef7c1abbc0 (diff) | |
video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
Instead of waiting for DC triple buffer to be cleared, this patch
changes to wait for a relevant DP sync flow end interrupt to come
when disabling sync BG flows. In this way, we align the implement
to the freescale internal IPUv3 driver. After applying this patch,
an uboot hang up issue at the arch_preboot_os() stage, where we
disable a relevant ipu display channel, is not observed any more on
some MX6DL platforms.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'drivers/video/ipu.h')
| -rw-r--r-- | drivers/video/ipu.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/video/ipu.h b/drivers/video/ipu.h index 3d2741f223..091b58fb47 100644 --- a/drivers/video/ipu.h +++ b/drivers/video/ipu.h @@ -176,6 +176,14 @@ typedef union { } ipu_channel_params_t; /* + * Enumeration of IPU interrupts. + */ +enum ipu_irq_line { + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_DC_FC_1 = 448 + 9, +}; + +/* * Bitfield of Display Interface signal polarities. */ typedef struct { |