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authorJernej Skrabec <jernej.skrabec@siol.net>2017-03-27 19:22:31 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-04-20 13:37:31 +0200
commit1ae5def6be484b0ee2c6ef72c750349b72342ac9 (patch)
treeff906db03e737fbb4b63a3b6a5551a3ba5c1d03f /drivers/video/sunxi
parent30ca20234e0cdce6e514ee6c1e73c97578efaea3 (diff)
sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs
This is needed for HDMI, which will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/video/sunxi')
-rw-r--r--drivers/video/sunxi/lcdc.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 8c8fb2e4ee..7d215b713e 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -74,9 +74,11 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
{
int bp, clk_delay, total, val;
+#ifndef CONFIG_SUNXI_DE2
/* Use tcon0 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON0);
+#endif
clk_delay = lcdc_get_clk_delay(mode, 0);
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
@@ -149,9 +151,11 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
{
int bp, clk_delay, total, val, yres;
+#ifndef CONFIG_SUNXI_DE2
/* Use tcon1 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
+#endif
clk_delay = lcdc_get_clk_delay(mode, 1);
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |