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| author | Jagan Teki <jagan@amarulasolutions.com> | 2018-08-02 15:43:02 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-01-18 22:19:08 +0530 |
| commit | e945816efbd3541f4a4e877e13221768f0b9f775 (patch) | |
| tree | 316d499293b728011e66f78a5fdf5473132497a0 /drivers/virtio | |
| parent | 99ba4308701c51dcf425dbef42c6f87fcc9c42a2 (diff) | |
clk: sunxi: Add Allwinner H3/H5 CLK driver
Add initial clock driver for Allwinner H3/H5.
- Implement USB bus and USB clocks via ccu_clk_gate table for
H3/H5, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for
H3/H5, so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/virtio')
0 files changed, 0 insertions, 0 deletions