diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-11-13 11:38:38 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-11-20 12:35:35 -0500 |
| commit | 2fa77bd12533e29e1b0f1742f66f258700715d52 (patch) | |
| tree | bdc9478627942cc191eab3f360ce37acd5a82f56 /drivers | |
| parent | 61927d286d2a4f4fd975967655590e8a59588533 (diff) | |
clk: meson: fix clk81 divider calculation
clk81 divider is 0 based (meaning that 0 value in the register means
divide by 1). Fix clk81 rate calculation for this.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk_meson.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c index 236d7342b7..c44858822d 100644 --- a/drivers/clk/clk_meson.c +++ b/drivers/clk/clk_meson.c @@ -600,7 +600,8 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) reg = readl(priv->addr + HHI_MPEG_CLK_CNTL); reg = reg & ((1 << 7) - 1); - return parent_rate / reg; + /* clk81 divider is zero based */ + return parent_rate / (reg + 1); } static long mpll_rate_from_params(unsigned long parent_rate, |