diff options
author | David Wu <david.wu@rock-chips.com> | 2018-01-13 14:01:45 +0800 |
---|---|---|
committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2018-01-28 17:12:37 +0100 |
commit | 301fff4e574d373a139dd47aceabc5b4259873da (patch) | |
tree | b80d65a0203c9a95aa1755e4c9ee41830d06a839 /drivers | |
parent | caf746172b30c0b54e12814f6360a68be6c431d9 (diff) |
rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver
Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/pinctrl/rockchip/pinctrl_rk3328.c | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index c74163e026..3c2253fdaf 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -17,6 +17,119 @@ DECLARE_GLOBAL_DATA_PTR; +enum { + /* GPIO0A_IOMUX */ + GPIO0A5_SEL_SHIFT = 10, + GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT, + GPIO0A5_I2C3_SCL = 2, + + GPIO0A6_SEL_SHIFT = 12, + GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT, + GPIO0A6_I2C3_SDA = 2, + + GPIO0A7_SEL_SHIFT = 14, + GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT, + GPIO0A7_EMMC_DATA0 = 2, + + GPIO0D6_SEL_SHIFT = 12, + GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_SDMMC0_PWRENM1 = 3, + + /* GPIO1A_IOMUX */ + GPIO1A0_SEL_SHIFT = 0, + GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, + GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, + + /* GPIO2A_IOMUX */ + GPIO2A0_SEL_SHIFT = 0, + GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, + GPIO2A0_UART2_TX_M1 = 1, + + GPIO2A1_SEL_SHIFT = 2, + GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, + GPIO2A1_UART2_RX_M1 = 1, + + GPIO2A2_SEL_SHIFT = 4, + GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT, + GPIO2A2_PWM_IR = 1, + + GPIO2A4_SEL_SHIFT = 8, + GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT, + GPIO2A4_PWM_0 = 1, + GPIO2A4_I2C1_SDA, + + GPIO2A5_SEL_SHIFT = 10, + GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT, + GPIO2A5_PWM_1 = 1, + GPIO2A5_I2C1_SCL, + + GPIO2A6_SEL_SHIFT = 12, + GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT, + GPIO2A6_PWM_2 = 1, + + GPIO2A7_SEL_SHIFT = 14, + GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_SDMMC0_PWRENM0, + + /* GPIO2BL_IOMUX */ + GPIO2BL0_SEL_SHIFT = 0, + GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT, + GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15, + + GPIO2BL3_SEL_SHIFT = 6, + GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT, + GPIO2BL3_SPI_CSN0_M0 = 1, + + GPIO2BL4_SEL_SHIFT = 8, + GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT, + GPIO2BL4_SPI_CSN1_M0 = 1, + + GPIO2BL5_SEL_SHIFT = 10, + GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT, + GPIO2BL5_I2C2_SDA = 1, + + GPIO2BL6_SEL_SHIFT = 12, + GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT, + GPIO2BL6_I2C2_SCL = 1, + + /* GPIO2D_IOMUX */ + GPIO2D0_SEL_SHIFT = 0, + GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT, + GPIO2D0_I2C0_SCL = 1, + + GPIO2D1_SEL_SHIFT = 2, + GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT, + GPIO2D1_I2C0_SDA = 1, + + GPIO2D4_SEL_SHIFT = 8, + GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT, + GPIO2D4_EMMC_DATA1234 = 0xaa, + + /* GPIO3C_IOMUX */ + GPIO3C0_SEL_SHIFT = 0, + GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT, + GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, + + /* COM_IOMUX */ + IOMUX_SEL_UART2_SHIFT = 0, + IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, + IOMUX_SEL_UART2_M0 = 0, + IOMUX_SEL_UART2_M1, + + IOMUX_SEL_SPI_SHIFT = 4, + IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, + IOMUX_SEL_SPI_M0 = 0, + IOMUX_SEL_SPI_M1, + IOMUX_SEL_SPI_M2, + + IOMUX_SEL_SDMMC_SHIFT = 7, + IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, + IOMUX_SEL_SDMMC_M0 = 0, + IOMUX_SEL_SDMMC_M1, +}; + struct rk3328_pinctrl_priv { struct rk3328_grf_regs *grf; }; |